40 Volt NMOS in a 0.5 μm standard CMOS process

Tsung Hsueh Lee; Pamela A. Abshire

doi:10.1109/ICSENS.2012.6411400

40 Volt NMOS in a 0.5 μm standard CMOS process

Tsung Hsueh Lee
, Pamela A. Abshire

Electrical Engineering

Stony Brook University

University of Maryland, College Park

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

High-voltage NMOS structures were implemented by introducing a lightly doped drain area to separate the channel and the drain diffusion area for NMOS transistors, and by extending the poly layer over the intervening field oxide. Majority and minority carrier guard rings were used to minimize parasitic effects and isolate the devices. A family of high-voltage devices was implemented with various geometries in order to determine the optimal dimensions. A total of 16 square and 16 circular devices were fabricated in a 0.5 μm standard 5V CMOS technology. Measurement results demonstrate breakdown voltages as high as 40 V in comparison with 10.9 V for a standard transistor in the same run. Breakdown voltages were found to be highest for circular structures in most cases. Circular structures also showed comparable transconductance to standard transistors. Detailed characterization such as Early voltage and threshold voltage are discussed.

Original language	English
Title of host publication	IEEE SENSORS 2012 - Proceedings
DOIs	https://doi.org/10.1109/ICSENS.2012.6411400
State	Published - 2012
Event	11th IEEE SENSORS 2012 Conference - Taipei, Taiwan, Province of China Duration: Oct 28 2012 → Oct 31 2012

Publication series

Name	Proceedings of IEEE Sensors

Conference

Conference	11th IEEE SENSORS 2012 Conference
Country/Territory	Taiwan, Province of China
City	Taipei
Period	10/28/12 → 10/31/12

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10.1109/ICSENS.2012.6411400

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@inproceedings{56ddabcd99d84074a703a0c0fb05aeff,

title = "40 Volt NMOS in a 0.5 μm standard CMOS process",

abstract = "High-voltage NMOS structures were implemented by introducing a lightly doped drain area to separate the channel and the drain diffusion area for NMOS transistors, and by extending the poly layer over the intervening field oxide. Majority and minority carrier guard rings were used to minimize parasitic effects and isolate the devices. A family of high-voltage devices was implemented with various geometries in order to determine the optimal dimensions. A total of 16 square and 16 circular devices were fabricated in a 0.5 μm standard 5V CMOS technology. Measurement results demonstrate breakdown voltages as high as 40 V in comparison with 10.9 V for a standard transistor in the same run. Breakdown voltages were found to be highest for circular structures in most cases. Circular structures also showed comparable transconductance to standard transistors. Detailed characterization such as Early voltage and threshold voltage are discussed.",

author = "Lee, \{Tsung Hsueh\} and Abshire, \{Pamela A.\}",

year = "2012",

doi = "10.1109/ICSENS.2012.6411400",

language = "English",

isbn = "9781457717659",

series = "Proceedings of IEEE Sensors",

booktitle = "IEEE SENSORS 2012 - Proceedings",

note = "11th IEEE SENSORS 2012 Conference ; Conference date: 28-10-2012 Through 31-10-2012",

}

TY - GEN

T1 - 40 Volt NMOS in a 0.5 μm standard CMOS process

AU - Lee, Tsung Hsueh

AU - Abshire, Pamela A.

PY - 2012

Y1 - 2012

N2 - High-voltage NMOS structures were implemented by introducing a lightly doped drain area to separate the channel and the drain diffusion area for NMOS transistors, and by extending the poly layer over the intervening field oxide. Majority and minority carrier guard rings were used to minimize parasitic effects and isolate the devices. A family of high-voltage devices was implemented with various geometries in order to determine the optimal dimensions. A total of 16 square and 16 circular devices were fabricated in a 0.5 μm standard 5V CMOS technology. Measurement results demonstrate breakdown voltages as high as 40 V in comparison with 10.9 V for a standard transistor in the same run. Breakdown voltages were found to be highest for circular structures in most cases. Circular structures also showed comparable transconductance to standard transistors. Detailed characterization such as Early voltage and threshold voltage are discussed.

AB - High-voltage NMOS structures were implemented by introducing a lightly doped drain area to separate the channel and the drain diffusion area for NMOS transistors, and by extending the poly layer over the intervening field oxide. Majority and minority carrier guard rings were used to minimize parasitic effects and isolate the devices. A family of high-voltage devices was implemented with various geometries in order to determine the optimal dimensions. A total of 16 square and 16 circular devices were fabricated in a 0.5 μm standard 5V CMOS technology. Measurement results demonstrate breakdown voltages as high as 40 V in comparison with 10.9 V for a standard transistor in the same run. Breakdown voltages were found to be highest for circular structures in most cases. Circular structures also showed comparable transconductance to standard transistors. Detailed characterization such as Early voltage and threshold voltage are discussed.

UR - https://www.scopus.com/pages/publications/84873958545

U2 - 10.1109/ICSENS.2012.6411400

DO - 10.1109/ICSENS.2012.6411400

M3 - Conference contribution

SN - 9781457717659

T3 - Proceedings of IEEE Sensors

BT - IEEE SENSORS 2012 - Proceedings

T2 - 11th IEEE SENSORS 2012 Conference

Y2 - 28 October 2012 through 31 October 2012

ER -

40 Volt NMOS in a 0.5 μm standard CMOS process

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