TY - GEN
T1 - A 10-bit 1-GHz 33-mW CMOS ADC
AU - Sahoo, Bibhu Datta
AU - Razavi, Behzad
PY - 2012
Y1 - 2012
N2 - A pipelined ADC digitally calibrates capacitor mismatches in its 4-bit first stage and the gain error in the first 5 stages. Using a one-stage op amp with a gain of 10 and realized in 65-nm CMOS technology, the ADC digitizes a 490-MHz input with an SNDR of 52.4 dB, achieving an FOM of 0.097pJ/conversion- step.
AB - A pipelined ADC digitally calibrates capacitor mismatches in its 4-bit first stage and the gain error in the first 5 stages. Using a one-stage op amp with a gain of 10 and realized in 65-nm CMOS technology, the ADC digitizes a 490-MHz input with an SNDR of 52.4 dB, achieving an FOM of 0.097pJ/conversion- step.
UR - https://www.scopus.com/pages/publications/84866627573
U2 - 10.1109/VLSIC.2012.6243774
DO - 10.1109/VLSIC.2012.6243774
M3 - Conference contribution
SN - 9781467308458
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - 30
EP - 31
BT - 2012 Symposium on VLSI Circuits, VLSIC 2012
T2 - 2012 Symposium on VLSI Circuits, VLSIC 2012
Y2 - 13 June 2012 through 15 June 2012
ER -