A 6V Embedded 90nm Silicon Nanocrystal Nonvolatile Memory

R. Muralidhar; R. F. Steimle; M. Sadd; R. Rao; C. T. Swift; E. J. Prinz; J. Yater; L. Grieve; K. Harber; B. Hradsky; S. Straub; B. Acred; W. Paulson; W. Chen; L. Parker; S. G.H. Anderson; M. Rossow; T. Merchant; M. Paransky; T. Huynh; D. Hadad; Ko Min Chang; B. E. White

A 6V Embedded 90nm Silicon Nanocrystal Nonvolatile Memory

R. Muralidhar
, R. F. Steimle
, M. Sadd
, R. Rao
, C. T. Swift
, E. J. Prinz
, J. Yater
, L. Grieve
, K. Harber
, B. Hradsky
, S. Straub
, B. Acred
, W. Paulson
, W. Chen
, L. Parker
, S. G.H. Anderson
, M. Rossow
, T. Merchant
, M. Paransky
, T. Huynh

D. Hadad, Ko Min Chang, B. E. White

Physics

Binghamton University

Motorola

Research output: Contribution to journal › Conference article › peer-review

65 Scopus citations

Abstract

The first functional 6V, 4Mb silicon nanocrystal based nonvolatile memory arrays using conventional 90nm and 0.25μm process technologies have been produced. The technology can be programmed and erased using conventional techniques in floating gate memories and can substantially reduce the cost of embedded Flash at the 90nm node and beyond.

Original language	English
Pages (from-to)	601-604
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
State	Published - 2003
Event	IEEE International Electron Devices Meeting - Washington, DC, United States Duration: Dec 8 2003 → Dec 10 2003

Cite this

Muralidhar, R., Steimle, R. F., Sadd, M., Rao, R., Swift, C. T., Prinz, E. J., Yater, J., Grieve, L., Harber, K., Hradsky, B., Straub, S., Acred, B., Paulson, W., Chen, W., Parker, L., Anderson, S. G. H., Rossow, M., Merchant, T., Paransky, M., ... White, B. E. (2003). A 6V Embedded 90nm Silicon Nanocrystal Nonvolatile Memory. Technical Digest - International Electron Devices Meeting, 601-604.

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title = "A 6V Embedded 90nm Silicon Nanocrystal Nonvolatile Memory",

abstract = "The first functional 6V, 4Mb silicon nanocrystal based nonvolatile memory arrays using conventional 90nm and 0.25μm process technologies have been produced. The technology can be programmed and erased using conventional techniques in floating gate memories and can substantially reduce the cost of embedded Flash at the 90nm node and beyond.",

author = "R. Muralidhar and Steimle, \{R. F.\} and M. Sadd and R. Rao and Swift, \{C. T.\} and Prinz, \{E. J.\} and J. Yater and L. Grieve and K. Harber and B. Hradsky and S. Straub and B. Acred and W. Paulson and W. Chen and L. Parker and Anderson, \{S. G.H.\} and M. Rossow and T. Merchant and M. Paransky and T. Huynh and D. Hadad and Chang, \{Ko Min\} and White, \{B. E.\}",

year = "2003",

language = "English",

pages = "601--604",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Electron Devices Meeting ; Conference date: 08-12-2003 Through 10-12-2003",

}

Muralidhar, R, Steimle, RF, Sadd, M, Rao, R, Swift, CT, Prinz, EJ, Yater, J, Grieve, L, Harber, K, Hradsky, B, Straub, S, Acred, B, Paulson, W, Chen, W, Parker, L, Anderson, SGH, Rossow, M, Merchant, T, Paransky, M, Huynh, T, Hadad, D, Chang, KM & White, BE 2003, 'A 6V Embedded 90nm Silicon Nanocrystal Nonvolatile Memory', Technical Digest - International Electron Devices Meeting, pp. 601-604.

TY - JOUR

T1 - A 6V Embedded 90nm Silicon Nanocrystal Nonvolatile Memory

AU - Muralidhar, R.

AU - Steimle, R. F.

AU - Sadd, M.

AU - Rao, R.

AU - Swift, C. T.

AU - Prinz, E. J.

AU - Yater, J.

AU - Grieve, L.

AU - Harber, K.

AU - Hradsky, B.

AU - Straub, S.

AU - Acred, B.

AU - Paulson, W.

AU - Chen, W.

AU - Parker, L.

AU - Anderson, S. G.H.

AU - Rossow, M.

AU - Merchant, T.

AU - Paransky, M.

AU - Huynh, T.

AU - Hadad, D.

AU - Chang, Ko Min

AU - White, B. E.

PY - 2003

Y1 - 2003

N2 - The first functional 6V, 4Mb silicon nanocrystal based nonvolatile memory arrays using conventional 90nm and 0.25μm process technologies have been produced. The technology can be programmed and erased using conventional techniques in floating gate memories and can substantially reduce the cost of embedded Flash at the 90nm node and beyond.

AB - The first functional 6V, 4Mb silicon nanocrystal based nonvolatile memory arrays using conventional 90nm and 0.25μm process technologies have been produced. The technology can be programmed and erased using conventional techniques in floating gate memories and can substantially reduce the cost of embedded Flash at the 90nm node and beyond.

UR - https://www.scopus.com/pages/publications/17644429462

M3 - Conference article

SN - 0163-1918

SP - 601

EP - 604

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - IEEE International Electron Devices Meeting

Y2 - 8 December 2003 through 10 December 2003

ER -

A 6V Embedded 90nm Silicon Nanocrystal Nonvolatile Memory

Abstract

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