A causal reasoning-based approach for analog circuit verification

Fanshu Jiao; Alex Doboli

doi:10.1109/SMACD.2015.7301711

A causal reasoning-based approach for analog circuit verification

Fanshu Jiao
, Alex Doboli

Electrical Engineering

Stony Brook University

Stony Brook University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper proposes a novel analog circuit verification approach using causal reasoning. To verify analog circuits, the flow begins with mining the causal reasoning steps (design plan) that produced the circuit, including starting ideas, design step sequence, and their justification [1]. Then, topological structures corresponding to the starting ideas and design step sequences are verified individually by replacing the related devices with ideal amplifier model. Circuit performance is evaluated through Spectre simulation. Comparing simulation results reveals incorrect functional issues and/or performance drawbacks (negative causes) of certain starting ideas or design steps, which might have been omitted during the design process. The paper discusses three operational amplifier designs realized in 0.2-μm CMOS technology to illustrate the verification approach.

Original language	English
Title of host publication	2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467391849
DOIs	https://doi.org/10.1109/SMACD.2015.7301711
State	Published - Oct 19 2015
Event	International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015 - Istanbul, Turkey Duration: Sep 7 2015 → Sep 9 2015

Publication series

Name	2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015

Conference

Conference	International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015
Country/Territory	Turkey
City	Istanbul
Period	09/7/15 → 09/9/15

Keywords

CMOS op-amp
analog verification
causal reasoning

Access to Document

10.1109/SMACD.2015.7301711

Cite this

Jiao, F., & Doboli, A. (2015). A causal reasoning-based approach for analog circuit verification. In 2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015 Article 7301711 (2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SMACD.2015.7301711

Jiao, Fanshu ; Doboli, Alex. / A causal reasoning-based approach for analog circuit verification. 2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015. Institute of Electrical and Electronics Engineers Inc., 2015. (2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015).

@inproceedings{12752542520644d5bdc8136e0ba7da0b,

title = "A causal reasoning-based approach for analog circuit verification",

abstract = "This paper proposes a novel analog circuit verification approach using causal reasoning. To verify analog circuits, the flow begins with mining the causal reasoning steps (design plan) that produced the circuit, including starting ideas, design step sequence, and their justification [1]. Then, topological structures corresponding to the starting ideas and design step sequences are verified individually by replacing the related devices with ideal amplifier model. Circuit performance is evaluated through Spectre simulation. Comparing simulation results reveals incorrect functional issues and/or performance drawbacks (negative causes) of certain starting ideas or design steps, which might have been omitted during the design process. The paper discusses three operational amplifier designs realized in 0.2-μm CMOS technology to illustrate the verification approach.",

keywords = "CMOS op-amp, analog verification, causal reasoning",

author = "Fanshu Jiao and Alex Doboli",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015 ; Conference date: 07-09-2015 Through 09-09-2015",

year = "2015",

month = oct,

day = "19",

doi = "10.1109/SMACD.2015.7301711",

language = "English",

series = "2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015",

}

Jiao, F & Doboli, A 2015, A causal reasoning-based approach for analog circuit verification. in 2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015., 7301711, 2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015, Institute of Electrical and Electronics Engineers Inc., International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015, Istanbul, Turkey, 09/7/15. https://doi.org/10.1109/SMACD.2015.7301711

A causal reasoning-based approach for analog circuit verification. / Jiao, Fanshu; Doboli, Alex.
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7301711 (2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A causal reasoning-based approach for analog circuit verification

AU - Jiao, Fanshu

AU - Doboli, Alex

PY - 2015/10/19

Y1 - 2015/10/19

N2 - This paper proposes a novel analog circuit verification approach using causal reasoning. To verify analog circuits, the flow begins with mining the causal reasoning steps (design plan) that produced the circuit, including starting ideas, design step sequence, and their justification [1]. Then, topological structures corresponding to the starting ideas and design step sequences are verified individually by replacing the related devices with ideal amplifier model. Circuit performance is evaluated through Spectre simulation. Comparing simulation results reveals incorrect functional issues and/or performance drawbacks (negative causes) of certain starting ideas or design steps, which might have been omitted during the design process. The paper discusses three operational amplifier designs realized in 0.2-μm CMOS technology to illustrate the verification approach.

AB - This paper proposes a novel analog circuit verification approach using causal reasoning. To verify analog circuits, the flow begins with mining the causal reasoning steps (design plan) that produced the circuit, including starting ideas, design step sequence, and their justification [1]. Then, topological structures corresponding to the starting ideas and design step sequences are verified individually by replacing the related devices with ideal amplifier model. Circuit performance is evaluated through Spectre simulation. Comparing simulation results reveals incorrect functional issues and/or performance drawbacks (negative causes) of certain starting ideas or design steps, which might have been omitted during the design process. The paper discusses three operational amplifier designs realized in 0.2-μm CMOS technology to illustrate the verification approach.

KW - CMOS op-amp

KW - analog verification

KW - causal reasoning

UR - https://www.scopus.com/pages/publications/84949595526

U2 - 10.1109/SMACD.2015.7301711

DO - 10.1109/SMACD.2015.7301711

M3 - Conference contribution

T3 - 2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015

BT - 2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015

Y2 - 7 September 2015 through 9 September 2015

ER -

Jiao F, Doboli A. A causal reasoning-based approach for analog circuit verification. In 2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7301711. (2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015). doi: 10.1109/SMACD.2015.7301711

A causal reasoning-based approach for analog circuit verification

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this