TY - GEN
T1 - A comparative study of some network subsystem organizations
AU - Ponomarev, D. V.
AU - Ghose, K.
N1 - Publisher Copyright: © 1998 IEEE.
PY - 1998
Y1 - 1998
N2 - The impact of alternative network subsystem design for realizing low end-To-end latencies and high network throughput in a switched LAN are studied in detail through simulation. These alternatives include choices in the disposition of the network interface card (NIC), DMA priorities and OS services. Our simulation model captures the delays of OS services/software layers, message copying DMAs and, in addition, models non-network related traffic on the I/O and memory buses introduced by paging and on-chip cache misses. In a conventional setup, with the NIC placed on the I/O bus, we show that changing traffic priorities on the memory bus to speed up the transfers between the NIC and the DRAM has little impact on overall latency and network throughput as the offered network traffic increases. Improving the speed of the I/O bus produces some performance gains. These performance gains are shown to be quite limited until message demultiplexing capabilities are added to the NIC. The best performance comes from the use of dual-ported DRAMs, with a dedicated connection between the NIC and the added port.
AB - The impact of alternative network subsystem design for realizing low end-To-end latencies and high network throughput in a switched LAN are studied in detail through simulation. These alternatives include choices in the disposition of the network interface card (NIC), DMA priorities and OS services. Our simulation model captures the delays of OS services/software layers, message copying DMAs and, in addition, models non-network related traffic on the I/O and memory buses introduced by paging and on-chip cache misses. In a conventional setup, with the NIC placed on the I/O bus, we show that changing traffic priorities on the memory bus to speed up the transfers between the NIC and the DRAM has little impact on overall latency and network throughput as the offered network traffic increases. Improving the speed of the I/O bus produces some performance gains. These performance gains are shown to be quite limited until message demultiplexing capabilities are added to the NIC. The best performance comes from the use of dual-ported DRAMs, with a dedicated connection between the NIC and the added port.
UR - https://www.scopus.com/pages/publications/77949829469
U2 - 10.1109/HIPC.1998.738019
DO - 10.1109/HIPC.1998.738019
M3 - Conference contribution
T3 - Proceedings - Symposium on Computer Architecture and High Performance Computing
SP - 436
EP - 443
BT - Proceedings - 5th International Conference on High Performance Computing, HiPC 1998
PB - IEEE Computer Society
T2 - 5th International Conference on High Performance Computing, HiPC 1998
Y2 - 17 December 1998 through 20 December 1998
ER -