A differential summing amplifier for analog VLSI systems

A. H. Titus; A. Gopalan

doi:10.1109/ISCAS.2002.1010387

A differential summing amplifier for analog VLSI systems

A. H. Titus
, A. Gopalan

Department of Biomedical Engineering

University at Buffalo

SUNY Buffalo

Research output: Contribution to journal › Article › peer-review

Abstract

We have designed, fabricated and tested an analog VLSI version of a differential summing amplifier that is based on the differential difference amplifier. This is a four-input amplifier with twelve minimal-sized transistors that covers an area that is 120 times less than previous differential difference amplifier designs, which makes it ideally suited for smart-pixel focal-plane arrays or analog neural networks that require high-density analog components of minimal size. The circuit has been tested and compared to larger versions using a chip fabricated through MOSIS using the AMI 1.5 micron two metal layer, double-poly analog process in a 2.2mm × 2.2mm tiny chip padframe. The experimental results show that its operation is favorable with the larger versions for use in open-loop mode, as a voltage follower, or output level-shifter.

Original language	English
Pages (from-to)	57-60
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	4
DOIs	https://doi.org/10.1109/ISCAS.2002.1010387
State	Published - 2002

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10.1109/ISCAS.2002.1010387

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title = "A differential summing amplifier for analog VLSI systems",

abstract = "We have designed, fabricated and tested an analog VLSI version of a differential summing amplifier that is based on the differential difference amplifier. This is a four-input amplifier with twelve minimal-sized transistors that covers an area that is 120 times less than previous differential difference amplifier designs, which makes it ideally suited for smart-pixel focal-plane arrays or analog neural networks that require high-density analog components of minimal size. The circuit has been tested and compared to larger versions using a chip fabricated through MOSIS using the AMI 1.5 micron two metal layer, double-poly analog process in a 2.2mm × 2.2mm tiny chip padframe. The experimental results show that its operation is favorable with the larger versions for use in open-loop mode, as a voltage follower, or output level-shifter.",

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AB - We have designed, fabricated and tested an analog VLSI version of a differential summing amplifier that is based on the differential difference amplifier. This is a four-input amplifier with twelve minimal-sized transistors that covers an area that is 120 times less than previous differential difference amplifier designs, which makes it ideally suited for smart-pixel focal-plane arrays or analog neural networks that require high-density analog components of minimal size. The circuit has been tested and compared to larger versions using a chip fabricated through MOSIS using the AMI 1.5 micron two metal layer, double-poly analog process in a 2.2mm × 2.2mm tiny chip padframe. The experimental results show that its operation is favorable with the larger versions for use in open-loop mode, as a voltage follower, or output level-shifter.

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JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

ER -

A differential summing amplifier for analog VLSI systems

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