@inproceedings{9eadd7873111433cae6d32d6b8627e7b,
title = "A fully parallel content addressable memory design using multi-bank structure",
abstract = "This paper presents a novel technique to reduce the power and latency in content-addressable memories (CAMs). The first technique is to discontinue the unnecessarily subsequent search-line precharge process based on pipelined matchline searching operation. Speed is improved significantly since search-line registers are comparing in parallel. Meanwhile, the power consumption is also significantly reduced by disabling the subsequential match-line and search-line precharge process. The second technique is to improve the speed further by implementing split-path match-line circuit into each match-line segment. Without additional complex peripheral circuits, our proposed design can achieve up to 47.78\% reduction in power consumption. At the same time, 95.4\% time can be shrunk as compared to Conventional NOR-type Architecture CAM design.",
keywords = "Content-addressable memory (CAM), high speed, low power, match-line, pipeline, search-line, split-path",
author = "Shixiong Jiang and Vijayalakshmi Saravanan and Pengzhan Yan and Ramalingam Sridhar",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 29th IEEE International System on Chip Conference, SOCC 2016 ; Conference date: 06-09-2016 Through 09-09-2016",
year = "2016",
month = jul,
day = "2",
doi = "10.1109/SOCC.2016.7905506",
language = "English",
series = "International System on Chip Conference",
publisher = "IEEE Computer Society",
pages = "338--343",
editor = "Karan Bhatia and Massimo Alioto and Danella Zhao and Andrew Marshall and Ramalingam Sridhar",
booktitle = "Proceedings - 29th IEEE International System on Chip Conference, SOCC 2016",
address = "United States",
}