@inproceedings{d9144e24d349442391683a8ae5dc2321,
title = "A gate leakage reduction strategy for sub-70nm memory circuits",
abstract = "The gate oxide thickness in sub-70nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistor operating modes. This gate leakage current, in addition to sub-threshold leakage, results in dramatic increase in total leakage power. Hence, efficient leakage reduction strategies that address the different dominant leakage components are necessary. In this paper, we analyze the use of NC-SRAM memory cell [9] for its effectiveness in gate leakage reduction. The technique provided around 60\% gate leakage savings in 65nm technology, with minimal impact on area, as compared to a conventional SRAM.",
keywords = "Dual-Vt, Gate leakage, Low leakage SRAM, Low power, Ultra deep submicron design",
author = "Praveen Elakkumanan and Charan Thondapu and Ramalingam Sridhar",
year = "2004",
doi = "10.1109/dcas.2004.1360446",
language = "English",
isbn = "0780387139",
series = "Proceedings of the 2004 IEEE Dallas/CAS Workshop: Implementation of High Performance Circuits. DCAS-04",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "145--148",
booktitle = "Proceedings of the 2004 IEEE Dallas/CAS Workshop",
address = "United States",
note = "Proceedings of the 2004 IEEE Dallas/CAS Workshop: Implementation of High Performance Circuits. DCAS-04 ; Conference date: 27-09-2004 Through 27-09-2004",
}