A New Approach to the Design of Built-in Self-Testing PLA's for High Fault Coverage

Four critical requirements can be identified for the built-in self testing of programmable logic arrays (BIST PLA's): 1) the test set to test the PLA as well as the output response be independent of the function of the PLA; 2) the test pattern generator (TPG) and the response evaluator (RE) circuits be simple in order to keep the extra logic overhead to a minimum; 3) the fault coverage of the PLA be within acceptable limit; 4) The speed of test application be high. There are a number of BIST designs in the literature, but they do not in general meet all these requirements. In this paper we propose a BIST PLA design to incorporate all the four goals stated above. We adopt a new approach based on counting crosspoints as opposed to the conventional parity technique. In our design, the TPG and RE circuits are simple and consist of shift registers and counters. The design requires a reorganization of the columns of the PLA on the basis of the number of crosspoints. An important feature of this design is its extremely high fault coverage. The coverage for multiple faults is higher than that of any known BIST designs whereas the single fault coverage of the proposed design is 100 percent. The proposed design is simple and can easily be incorporated into existing computer-aided design systems.