A Novel PMOS SOI Polysilicon Transistor

James R. Pfiester; James D. Hayden; Craig D. Gunderson; Jung Hui Lin; Vidya Kaushik

doi:10.1109/55.57930

A Novel PMOS SOI Polysilicon Transistor

James R. Pfiester
, James D. Hayden
, Craig D. Gunderson
, Jung Hui Lin
, Vidya Kaushik

NY Creates Research Foundation

NY Creates

Motorola

Research output: Contribution to journal › Article › peer-review

Abstract

An advanced SOI PMOS polysilicon transistor, which features an inverted gate electrode and self-aligned source/drain and gate/channel regions, has been developed and characterized. Selective oxidation is used to form self-aligned thin polysilicon channel regions with thicker source/drain polysilicon regions. Excellent short-channel device characteristics were obtained, which indicate complete depletion of the thin polysilicon channel region.

Original language	English
Pages (from-to)	349-351
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	11
Issue number	8
DOIs	https://doi.org/10.1109/55.57930
State	Published - Aug 1990

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title = "A Novel PMOS SOI Polysilicon Transistor",

abstract = "An advanced SOI PMOS polysilicon transistor, which features an inverted gate electrode and self-aligned source/drain and gate/channel regions, has been developed and characterized. Selective oxidation is used to form self-aligned thin polysilicon channel regions with thicker source/drain polysilicon regions. Excellent short-channel device characteristics were obtained, which indicate complete depletion of the thin polysilicon channel region.",

author = "Pfiester, \{James R.\} and Hayden, \{James D.\} and Gunderson, \{Craig D.\} and Lin, \{Jung Hui\} and Vidya Kaushik",

year = "1990",

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doi = "10.1109/55.57930",

language = "English",

volume = "11",

pages = "349--351",

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AU - Pfiester, James R.

AU - Hayden, James D.

AU - Gunderson, Craig D.

AU - Lin, Jung Hui

AU - Kaushik, Vidya

PY - 1990/8

Y1 - 1990/8

N2 - An advanced SOI PMOS polysilicon transistor, which features an inverted gate electrode and self-aligned source/drain and gate/channel regions, has been developed and characterized. Selective oxidation is used to form self-aligned thin polysilicon channel regions with thicker source/drain polysilicon regions. Excellent short-channel device characteristics were obtained, which indicate complete depletion of the thin polysilicon channel region.

AB - An advanced SOI PMOS polysilicon transistor, which features an inverted gate electrode and self-aligned source/drain and gate/channel regions, has been developed and characterized. Selective oxidation is used to form self-aligned thin polysilicon channel regions with thicker source/drain polysilicon regions. Excellent short-channel device characteristics were obtained, which indicate complete depletion of the thin polysilicon channel region.

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U2 - 10.1109/55.57930

DO - 10.1109/55.57930

M3 - Article

SN - 0741-3106

VL - 11

SP - 349

EP - 351

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 8

ER -

A Novel PMOS SOI Polysilicon Transistor

Abstract

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