@inproceedings{6f6167a4eb484f528e933e591a377da4,
title = "A Systematic Approach to Sizing Capacitors in Split-SAR ADC to Achieve Optimum Redundancy",
abstract = "This paper proposes a systematic way of sizing capacitors in a split-Successive Approximation Register (SAR) analog-to-digital converter (ADC) so as to achieve optimum redundancy that can take care of comparator noise, comparator offset, and digital-to-analog converter (DAC) finite settling. The capacitor sizing technique to optimally distribute redundancy across all bit-cycling phases, has been demonstrated with system-level simulation using MATLAB for split-SAR with one, two, and three bridge-capacitors. The proposed technique of sizing capacitors to achieve optimum redundancy at every bit-cycling step can be easily extended for split-SAR with arbitrary number of bridge-capacitors.",
keywords = "capacitor sizing, generalized non-binary, non-binary, redundancy, split-SAR",
author = "Alok Keshattiwar and Sahoo, \{Bibhu Datta\}",
note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 62nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2019 ; Conference date: 04-08-2019 Through 07-08-2019",
year = "2019",
month = aug,
doi = "10.1109/MWSCAS.2019.8884954",
language = "English",
series = "Midwest Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "117--120",
booktitle = "2019 IEEE 62nd International Midwest Symposium on Circuits and Systems, MWSCAS 2019",
address = "United States",
}