Achieving Theoretical Limit of SFDR in Pipelined ADCs

In pipelined analog-to-digital converters (ADCs), the spurious free dynamic range (SFDR) and signal-to-noise ratio depend strongly on the precision with which the interstage gain and capacitor mismatch terms are estimated using digital calibration techniques. This paper introduces a dithering-based calibration technique, which facilitates accurate estimation of the interstage gain and capacitor mismatch term with minimal hardware overhead, thus realizing pipelined ADCs that achieve the theoretical maximum SFDR. The proposed technique is validated both at system level using MATLAB and then at circuit level. A prototype 12-bit pipelined ADC operating at 500 MHz was designed in 55-nm global foundry LP-CMOS process. The prototype 12-bit ADC realized with op amp that have open-loop gains as low as 54 dB, but linearity ≈100 dB achieves an SFDR of 100.13 dB when calibrated using the proposed technique.