TY - GEN
T1 - Advances in High Performance RDL Technologies for Enabling IO Density of 500 IOs/mm/layer and 8-μm IO Pitch Using Low-k Dielectrics
AU - Liu, Fuhan
AU - Zhang, Rui
AU - Deprospo, Bartlet H.
AU - Dwarakanath, Shreya
AU - Nimbalkar, Pratik
AU - Ravichandran, Siddharth
AU - Weyers, David
AU - Kathaperumal, Mohanalingam
AU - Tummala, Rao R.
AU - Swaminathan, Madhavan
N1 - Publisher Copyright: © 2020 IEEE.
PY - 2020/6
Y1 - 2020/6
N2 - Currently, the IC industry has been steadily advancing towards 7 nm and 5 nm nodes with further reductions projected in the near future to progressively create large number of inputs and outputs (IOs) at finer pitch. Today the high-density interconnect (HDI) organic redistribution layer (RDL) can only achieve an IO density of about 40 IOs per mm per layer with line and space of 6 μm and microvia diameter of 20 μm at 50 μm pitch. However, to achieve further increases in IO density, RDL with 1 μm routing lines and spaces together with 1 to 2 μm diameter microvias are required. Such advances in the RDL technology are of great importance to accomplish IO densities of 500 IOs/mm/layer to enable high bandwidths of 500 Gb/s at low cost. In this paper we present the latest progress at the Packaging Research Center, Georgia Institute of Technology in the following 4 key areas.1. Fine line photolithography: Various methods that can achieve 1 μm critical dimension (CD) are discussed and recent results on 1 μm L/S using both dry film and liquid photoresists together with advanced lithographic tools are presented.2. Small microvia creation: Microvia is the most important barrier limiting the RDL to achieve high IO density and fine IO pitch. In this paper, microvia diameter scaling down to 2 μm along with the feasibility to achieve 1 μm and via pitch of 4 to 8 μm using both photo and picosecond pulsed UV laser will be presented.3. Low Dk and Low Df dielectric materials: Dielectric material layers are an important part of RDL. For achieving multi-functional high speed and/or low loss systems and modules, dielectric layers with low Dk and/or low Df materials are critical. The material requirements, availability and process challenges will be addressed in this paper.4. Process methodology: The semi-additive process (SAP) has been the process of record for RDL fabrication. In this paper, the conventional SAP and its modifications such as modified-SAP (m-SAP) and advanced SAP (a-SAP) together with alternative organic damascene process (ODP) along with back-end- of-line (BEOL) will be reviewed and compared.Finally, considerations for future trends are presented.
AB - Currently, the IC industry has been steadily advancing towards 7 nm and 5 nm nodes with further reductions projected in the near future to progressively create large number of inputs and outputs (IOs) at finer pitch. Today the high-density interconnect (HDI) organic redistribution layer (RDL) can only achieve an IO density of about 40 IOs per mm per layer with line and space of 6 μm and microvia diameter of 20 μm at 50 μm pitch. However, to achieve further increases in IO density, RDL with 1 μm routing lines and spaces together with 1 to 2 μm diameter microvias are required. Such advances in the RDL technology are of great importance to accomplish IO densities of 500 IOs/mm/layer to enable high bandwidths of 500 Gb/s at low cost. In this paper we present the latest progress at the Packaging Research Center, Georgia Institute of Technology in the following 4 key areas.1. Fine line photolithography: Various methods that can achieve 1 μm critical dimension (CD) are discussed and recent results on 1 μm L/S using both dry film and liquid photoresists together with advanced lithographic tools are presented.2. Small microvia creation: Microvia is the most important barrier limiting the RDL to achieve high IO density and fine IO pitch. In this paper, microvia diameter scaling down to 2 μm along with the feasibility to achieve 1 μm and via pitch of 4 to 8 μm using both photo and picosecond pulsed UV laser will be presented.3. Low Dk and Low Df dielectric materials: Dielectric material layers are an important part of RDL. For achieving multi-functional high speed and/or low loss systems and modules, dielectric layers with low Dk and/or low Df materials are critical. The material requirements, availability and process challenges will be addressed in this paper.4. Process methodology: The semi-additive process (SAP) has been the process of record for RDL fabrication. In this paper, the conventional SAP and its modifications such as modified-SAP (m-SAP) and advanced SAP (a-SAP) together with alternative organic damascene process (ODP) along with back-end- of-line (BEOL) will be reviewed and compared.Finally, considerations for future trends are presented.
KW - Dielectrics
KW - IO Density
KW - IO Pitch
KW - Microvia
KW - Photolithography
KW - RDL
UR - https://www.scopus.com/pages/publications/85090287688
U2 - 10.1109/ECTC32862.2020.00182
DO - 10.1109/ECTC32862.2020.00182
M3 - Conference contribution
T3 - Proceedings - Electronic Components and Technology Conference
SP - 1132
EP - 1139
BT - Proceedings - IEEE 70th Electronic Components and Technology Conference, ECTC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 70th IEEE Electronic Components and Technology Conference, ECTC 2020
Y2 - 3 June 2020 through 30 June 2020
ER -