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An approach to compensate for capacitor mismatches in SAR ADC using multiple comparisons

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Abstract

This paper presents a new approach to compensate for mismatches in capacitor array of a successive-approximation-register (SAR) analog-to-digital converter (ADC). The proposed approach employs multiple comparisons per bit cycle before making a decision. Instead of taking the majority vote as has been done in existing work, different threshold values are used to compensate for the transition level reference voltage errors caused by capacitor mismatches. A closed-form expression of the effective comparator noise as a function of different threshold value shifts and number of votes is derived. Simulation results of an 8-bit SAR ADC show that the proposed scheme achieves near ideal ENOB and SFDR performance.

Original languageEnglish
Title of host publication2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728103976
DOIs
StatePublished - 2019
Event2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan
Duration: May 26 2019May 29 2019

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2019-May

Conference

Conference2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
Country/TerritoryJapan
CitySapporo
Period05/26/1905/29/19

Keywords

  • Majority vote
  • Multiple comparison
  • SAR ADC
  • Stochastic self calibration

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