TY - GEN
T1 - An Optically Sampled ADC in 3D Integrated Silicon-Photonics/65nm CMOS
AU - Mehta, Nandish
AU - Su, Zhan
AU - Timurdogan, Erman
AU - Notaros, Jelena
AU - Wilcox, Russel
AU - Poulton, Christopher
AU - Baiocco, Christopher
AU - Fahrenkopf, Nicholas
AU - Kruger, Seth
AU - Ngai, Tat
AU - Timalsina, Yukta
AU - Watts, Michael
AU - Stojanovic, Vladimir
N1 - Publisher Copyright: © 2020 IEEE.
PY - 2020/6
Y1 - 2020/6
N2 - The accuracy of conventional ADCs for high-frequency input signals is mainly limited by the sampling clock jitter. To address this issue, this paper demonstrates an ADC that uses low-jitter (< 26\ fsrms) optical pulses to sample the input signal. A prototype two-channel ADC is realized in a 3D integrated platform with 65 nm CMOS and silicon-photonics connected using high-density TOVs. With optical pulses spaced at 250 ps (4 GS/s effective sampling rate), the ADC achieves SNDR of 40 dB near DC and 37 dB at 45 GHz input.
AB - The accuracy of conventional ADCs for high-frequency input signals is mainly limited by the sampling clock jitter. To address this issue, this paper demonstrates an ADC that uses low-jitter (< 26\ fsrms) optical pulses to sample the input signal. A prototype two-channel ADC is realized in a 3D integrated platform with 65 nm CMOS and silicon-photonics connected using high-density TOVs. With optical pulses spaced at 250 ps (4 GS/s effective sampling rate), the ADC achieves SNDR of 40 dB near DC and 37 dB at 45 GHz input.
UR - https://www.scopus.com/pages/publications/85098129131
U2 - 10.1109/VLSITechnology18217.2020.9265101
DO - 10.1109/VLSITechnology18217.2020.9265101
M3 - Conference contribution
T3 - Digest of Technical Papers - Symposium on VLSI Technology
BT - 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020
Y2 - 16 June 2020 through 19 June 2020
ER -