TY - GEN
T1 - An overview of digital calibration techniques for pipelined ADCs
AU - Sahoo, Bibhudatta
N1 - Publisher Copyright: © 2014 IEEE.
PY - 2014/9/23
Y1 - 2014/9/23
N2 - As device dimensions and supply voltage are shrinking, the design of high-speed and high-resolution analog-to-digital converters (ADCs) is getting more and more challenging. Since the shrinking device sizes enable high-speed and low-power digital circuits, there has been a trend to use digital circuits to estimate and correct for the analog circuit nonidealities (i.e. calibrate) to realize high-performance ADCs. This summary paper enumerates some of the digital techniques that have been adopted in the past two decades to realize high-speed high-resolution pipelined ADCs, which are typically used in communication and imaging applications.
AB - As device dimensions and supply voltage are shrinking, the design of high-speed and high-resolution analog-to-digital converters (ADCs) is getting more and more challenging. Since the shrinking device sizes enable high-speed and low-power digital circuits, there has been a trend to use digital circuits to estimate and correct for the analog circuit nonidealities (i.e. calibrate) to realize high-performance ADCs. This summary paper enumerates some of the digital techniques that have been adopted in the past two decades to realize high-speed high-resolution pipelined ADCs, which are typically used in communication and imaging applications.
UR - https://www.scopus.com/pages/publications/84908475747
U2 - 10.1109/MWSCAS.2014.6908601
DO - 10.1109/MWSCAS.2014.6908601
M3 - Conference contribution
T3 - Midwest Symposium on Circuits and Systems
SP - 1061
EP - 1064
BT - 2014 IEEE 57th International Midwest Symposium on Circuits and Systems, MWSCAS 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 IEEE 57th International Midwest Symposium on Circuits and Systems, MWSCAS 2014
Y2 - 3 August 2014 through 6 August 2014
ER -