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Architectural support for dynamic linking

  • Varun Agrawal
  • , Abhiroop Dabral
  • , Tapti Palit
  • , Yongming Shen
  • , Michael Ferdman
  • Stony Brook University

Research output: Contribution to journalArticlepeer-review

11 Scopus citations

Abstract

All software in use today relies on libraries, including standard libraries (e.g., C, C++) and application-specific libraries (e.g., libxml, libpng). Most libraries are loaded in memory and dynamically linked when programs are launched, resolving symbol addresses across the applications and libraries. Dynamic linking has many benefits: It allows code to be reused between applications, conserves memory (because only one copy of a library is kept in memory for all the applications that share it), and allows libraries to be patched and updated without modifying programs, among numerous other benefits. However, these benefits come at the cost of performance. For every call made to a function in a dynamically linked library, a trampoline is used to read the function address from a lookup table and branch to the function, incurring memory load and branch operations. Static linking avoids this performance penalty, but loses all the benefits of dynamic linking. Given its myriad benefits, dynamic linking is the predominant choice today, despite the performance cost. In this work, we propose a speculative hardware mechanism to optimize dynamic linking by avoiding executing the trampolines for library function calls, providing the benefits of dynamic linking with the performance of static linking. Speculatively skipping the memory load and branch operations of the library call trampolines improves performance by reducing the number of executed instructions and gains additional performance by reducing pressure on the instruction and data caches, TLBs, and branch predictors. Because the indirect targets of library call trampolines do not change during program execution, our speculative mechanism never misspeculates in practice. We evaluate our technique on real hardware with production software and observe up to 4% speedup using only 1.5KB of on-chip storage.

Original languageEnglish
Pages (from-to)691-702
Number of pages12
JournalACM SIGPLAN Notices
Volume50
Issue number4
DOIs
StatePublished - Apr 2015

Keywords

  • Branch prediction
  • Dynamic linking
  • Hardware memoization
  • Instruction elision

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