Abstract
Over the last five years, the large scale integrated circuit placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved impressive empirical results. These advances have been supported by a nontrivial bench-marking infrastructure, and future achievements are set to draw on benchmarking as well. In this paper, we review motivations for benchmarking, especially for commercial electronic design automation, analyze available benchmarks, and point out major pitfalls in benchmarking. Our empirical data offers perhaps the first comprehensive evaluation of several leading large-scale placers on multiple benchmark families. We outline major outstanding problems and discuss the future of placement bench-marking. Furthermore, we attempt to extrapolate our experience to circuit layout tasks beyond placement.
| Original language | English |
|---|---|
| Pages (from-to) | 472-487 |
| Number of pages | 16 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | 23 |
| Issue number | 4 |
| DOIs | |
| State | Published - Apr 2004 |
Keywords
- Algorithms
- Design automation
- Design methodology
- Documentation
- Integrated circuit design
- Integrated circuit layout
- Measurement
- Routing, timing
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