Circuit challenges and proposed solutions targeting nanometer technologies

Radu M. Secareanu; Marquis Jones; Michael Sadd; Bruce White; Papu Maniar

doi:10.1109/ASIC.2001.954721

Circuit challenges and proposed solutions targeting nanometer technologies

Radu M. Secareanu
, Marquis Jones
, Michael Sadd
, Bruce White
, Papu Maniar

Physics

Binghamton University

Motorola

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

Presently, R&D organizations of leading semiconductor companies are focusing their efforts on developing devices, technologies, and applications for below the 100 nanometer feature size. Specific device, circuit, and system challenges for the 30 nanometer feature size in present R&D focus at Motorola, are analyzed in this paper. Circuit solutions that will ease the device and technology development while allowing the stringent device, circuit, and system performance requirements for the 30 nanometer node to be met, are proposed.

Original language	English
Pages (from-to)	325-329
Number of pages	5
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs	https://doi.org/10.1109/ASIC.2001.954721
State	Published - 2001

Access to Document

10.1109/ASIC.2001.954721

Cite this

@article{dd92e72c1f794f3a91b18fe271a04fbd,

title = "Circuit challenges and proposed solutions targeting nanometer technologies",

abstract = "Presently, R\&D organizations of leading semiconductor companies are focusing their efforts on developing devices, technologies, and applications for below the 100 nanometer feature size. Specific device, circuit, and system challenges for the 30 nanometer feature size in present R\&D focus at Motorola, are analyzed in this paper. Circuit solutions that will ease the device and technology development while allowing the stringent device, circuit, and system performance requirements for the 30 nanometer node to be met, are proposed.",

author = "Secareanu, \{Radu M.\} and Marquis Jones and Michael Sadd and Bruce White and Papu Maniar",

year = "2001",

doi = "10.1109/ASIC.2001.954721",

language = "English",

pages = "325--329",

journal = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

issn = "1063-0988",

}

TY - JOUR

T1 - Circuit challenges and proposed solutions targeting nanometer technologies

AU - Secareanu, Radu M.

AU - Jones, Marquis

AU - Sadd, Michael

AU - White, Bruce

AU - Maniar, Papu

PY - 2001

Y1 - 2001

N2 - Presently, R&D organizations of leading semiconductor companies are focusing their efforts on developing devices, technologies, and applications for below the 100 nanometer feature size. Specific device, circuit, and system challenges for the 30 nanometer feature size in present R&D focus at Motorola, are analyzed in this paper. Circuit solutions that will ease the device and technology development while allowing the stringent device, circuit, and system performance requirements for the 30 nanometer node to be met, are proposed.

AB - Presently, R&D organizations of leading semiconductor companies are focusing their efforts on developing devices, technologies, and applications for below the 100 nanometer feature size. Specific device, circuit, and system challenges for the 30 nanometer feature size in present R&D focus at Motorola, are analyzed in this paper. Circuit solutions that will ease the device and technology development while allowing the stringent device, circuit, and system performance requirements for the 30 nanometer node to be met, are proposed.

UR - https://www.scopus.com/pages/publications/0034781589

U2 - 10.1109/ASIC.2001.954721

DO - 10.1109/ASIC.2001.954721

M3 - Article

SN - 1063-0988

SP - 325

EP - 329

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

ER -

Circuit challenges and proposed solutions targeting nanometer technologies

Abstract

Access to Document

Other files and links

Fingerprint

Cite this