CMOS wave-pipelined image processor for real-time morphology

This paper presents the implementation of a high-speed morphological image processor using CMOS wave-pipelining. A modular and expandable architecture, based on Wave-pipelined Transmission Gate Logic, has been developed for gray-scale and binary morphological operators. Using this architecture, 3×3 (2-dimensional) structuring element binary dilation and erosion units, and a two-stage morphological skeleton transform filter have been implemented in CMOS 1.2 μm technology. The operating frequency is 333 MHz, which exceeds the speeds reported in literature for this functionality. Simulation results indicate a speed-up of 4-5 compared to non-pipelined processor implementations. The wave-pipelined implementation also offers a significant reduction in latency and hardware complexity compared to regular pipelined architectures.