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Defect passivation with fluorine in a TaxCy/High-K gate stack for enhanced device threshold voltage stability and performance

  • H. H. Tseng
  • , P. J. Tobin
  • , E. A. Hebert
  • , S. Kalpat
  • , M. E. Ramón
  • , L. Fonseca
  • , Z. X. Jiang
  • , J. K. Schaeffer
  • , R. I. Hegde
  • , D. H. Triyoso
  • , D. C. Gilmer
  • , W. J. Taylor
  • , C. C. Capasso
  • , O. Adetutu
  • , D. Sing
  • , J. Conner
  • , E. Luckowski
  • , B. W. Chan
  • , A. Haggag
  • , S. Backer
  • R. Noble, M. Jahanbani, Y. H. Chiu, B. E. White
  • Freescale Semiconductor
  • Taiwan Semiconductor Manufacturing Company

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

20 Scopus citations

Abstract

Using a novel fluorinated TaxCy/High-K gate stack, we show breakthrough device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem and performance degradation for High-K is a concern. The novel fluorinated gate stack device exceeds the PBTI and NBTI targets with sufficient margin and has electron mobility comparable to the best polySi/SiON device on bulk Si reported so far.

Original languageEnglish
Title of host publicationIEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
Pages696-699
Number of pages4
StatePublished - 2005
EventIEEE International Electron Devices Meeting, 2005 IEDM - Washington, DC, MD, United States
Duration: Dec 5 2005Dec 7 2005

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2005

Conference

ConferenceIEEE International Electron Devices Meeting, 2005 IEDM
Country/TerritoryUnited States
CityWashington, DC, MD
Period12/5/0512/7/05

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