Demonstration and analysis of a 600 V, 10 A, 4H-SiC lateral single RESURF MOSFET for power ICs applications

This paper reports the demonstration of a 600 V 4H-SiC lateral MOSFET with a large current handling capability (10 A). To achieve a high breakdown voltage in a lateral architecture, a REduced SURface Field (RESURF) structure was implemented to alleviate surface electric field crowding. A single RESURF (P-top) design on an N-drift on a 6-in. N+ substrate demonstrated a voltage supporting capability of 120 V/μm, resulting in a breakdown voltage of 600 V. The total width of 198 mm for the interdigitated gate fingers was designed to accomplish the high current capability. It turned out that, for relatively low voltage SiC lateral MOSFETs (<600 V), more focus needs to be placed on achieving a low channel, contact, metal, and JFET region resistance than a low drift layer resistance to further improve the on-resistance. Device design, fabrication, and electrical characterization of the proposed 600 V, 10 A, 4H-SiC lateral single RESURF MOSFETs are discussed in this paper.