Design and characterization of high-voltage NMOS structures in a 0.5 μm standard CMOS process

High-voltage NMOS structures are implemented by introducing N-well and field oxide buffer regions in order to separate the channel and the drain diffusion area for NMOS transistors. A family of high-voltage devices are implemented with various geometries in order to determine the optimal dimensions. A total of 16 rectangular and 47 circular devices were fabricated in a 0.5 μm standard CMOS technology. Measurement results demonstrate breakdown voltages of > 40 V in comparison with 12.5 V for a standard transistor in the same technology. Breakdown voltages are found to be highest for drain-centered circular structures, and nearly as high for rectangular structures. Drain-centered circular structures also show comparable transconductance and specific ON resistance to standard transistors. Detailed characterization such as Early voltage, threshold voltage, and breakdown mechanism are discussed.