Abstract
This article focuses on providing the laminated busbar design guidance for a three-level T-type neutral-point-clamped (3L-TNPC) inverter to achieve low stray inductance and balanced inductance distribution between paralleled power switches. As a result, equalized dynamic current sharing can be accomplished. To discover the design strategy, this article first derives the mutual-inductance-decoupled equivalent circuit for 3L-TNPC. Then, the effects of each inductance item on switching performance can be unveiled, and the parametric targets are then summarized. Accordingly, the busbar design considerations are discussed. A step-by-step busbar design procedure to achieve the aforementioned design targets is provided in the next. The design procedure starts from 2-D optimization to achieve the optimal component and terminal allocation, and then, it increases the optimization degree to 3-D. Using this design procedure, we proposed a novel double-side-end busbar structure to achieve the busbar stray inductance of 12.7 nH and the inductance differences between the paralleled switches to be less than 2 nH. Extensive experiments are carried out in the end to evaluate the design procedure and demonstrate the performance of the busbar.
| Original language | English |
|---|---|
| Article number | 8869812 |
| Pages (from-to) | 395-406 |
| Number of pages | 12 |
| Journal | IEEE Journal of Emerging and Selected Topics in Power Electronics |
| Volume | 8 |
| Issue number | 1 |
| DOIs | |
| State | Published - Mar 2020 |
Keywords
- Current sharing
- SiC MOSFET
- laminated busbar
- stray inductance
- three-level T-type neutral-point-clamped (3L-TNPC) inverter
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