Design and Fabrication Approaches of 400-600 v 4H-SiC Lateral MOSFETs for Emerging Power ICs Application

This article reports the demonstration and fabrication of 400-600 V, 4H-SiC lateral MOSFETs on 6-in, N+ substrates. The P-top was implanted on an N+ drift region to create a single reduced surface field (RESURF) structure to alleviate the electric field on the surface. The different layout methodologies (source-centered and drain-centered) for making lateral MOSFETs are discussed. The process and design split, such as rapid thermal anneal (RTA) temperatures (900 °C and 1000 °C), different channel designs [accumulation-mode (ACCU) and inversion-mode (INV)], and channel lengths were varied and experimentally analyzed to optimize the device performance. It was confirmed that channel components (channel design and channel length) and RTA temperature are the key ingredients to improve the forward characteristic of the lateral MOSFETs. With the gate to drain length (Lgd) of 5 μm, the breakdown voltage of 600 V was achieved with a voltage supporting capability of 120 V μm. On the other hand, a lateral MOSFET with Lgd of 2.5 μm and with a further reduced channel length (Lch= 0.3 μm), a record specific ON-resistance of 7.7 m Ω-cm2 and breakdown voltage of 450 V were achieved. Device design, layout, fabrication, and electrical characteristics of the 400-600 V, 4H-SiC lateral MOSFETs are discussed and reported.