Design of a Low Parasitic Inductance Paralleled Module for 8.56 kV β-Ga₂O₃MOSFET

Based on the parameters of a lab sample β-Ga2O3 MOSFET die, a laminated structure is proposed to reduce the parasitic inductance of a two-parallel MOSFET module. The inductance of the proposed laminated module is reduced to half that of the non-laminated module. Subsequently, a laminated double pulse test (DPT) circuit board with a symmetric structure is designed to reduce the PCB inductance and improve the performance of current sharing. Then, PCB thermal vias and multi-objective optimized heat sink are used in four-parallel Ga2O3 MOSFET dies to improve heat dissipation efficiency. The improved heat sink design is validated through steady-state thermal simulation, showing a maximum temperature reduction of 12.5 C for the MOSFETs, which is 15.2% lower compared to the model without thermal vias and optimized heat sink.