Design study of (2 × 2) core architecture for matrix multiplications via Programmable Graph Architecture

Jun Hee Mun; Muling Peng; Sangjin Hong; Alex Doboli; K. Wendy Tang

Design study of (2 × 2) core architecture for matrix multiplications via Programmable Graph Architecture

Jun Hee Mun
, Muling Peng
, Sangjin Hong
, Alex Doboli
, K. Wendy Tang

Electrical Engineering

Stony Brook University

Stony Brook University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a 2 × 2 core architecture for matrix multiplications via the Programmable Graph Architecture approach proposed earlier. A larger matrix-matrix multiplication can be carried out through sub-matrix decomposition. The iterative operation is completely performed with simple arithmetic operations and memory accesses. The core architecture is structurally described using Verilog and its functionality has been verified. Performance of the operation and factors influencing the execution are analyzed.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, 2005 SOCC
Editors	D. Ha, R. Krishnamurthy, S. Kim, A. Marshall
Pages	87-88
Number of pages	2
State	Published - 2005
Event	2005 IEEE International SOC Conference - Herndon, VA, United States Duration: Sep 25 2005 → Sep 28 2005

Publication series

Name	Proceedings - IEEE International SOC Conference

Conference

Conference	2005 IEEE International SOC Conference
Country/Territory	United States
City	Herndon, VA
Period	09/25/05 → 09/28/05

Cite this

@inproceedings{b96e6561c7ef487bb102be5a33b12c5d,

title = "Design study of (2 × 2) core architecture for matrix multiplications via Programmable Graph Architecture",

abstract = "This paper presents a 2 × 2 core architecture for matrix multiplications via the Programmable Graph Architecture approach proposed earlier. A larger matrix-matrix multiplication can be carried out through sub-matrix decomposition. The iterative operation is completely performed with simple arithmetic operations and memory accesses. The core architecture is structurally described using Verilog and its functionality has been verified. Performance of the operation and factors influencing the execution are analyzed.",

author = "Mun, \{Jun Hee\} and Muling Peng and Sangjin Hong and Alex Doboli and Tang, \{K. Wendy\}",

year = "2005",

language = "English",

isbn = "0780392647",

series = "Proceedings - IEEE International SOC Conference",

pages = "87--88",

editor = "D. Ha and R. Krishnamurthy and S. Kim and A. Marshall",

booktitle = "Proceedings - IEEE International SOC Conference, 2005 SOCC",

note = "2005 IEEE International SOC Conference ; Conference date: 25-09-2005 Through 28-09-2005",

}

Mun, JH, Peng, M, Hong, S , Doboli, A & Tang, KW 2005, Design study of (2 × 2) core architecture for matrix multiplications via Programmable Graph Architecture. in D Ha, R Krishnamurthy, S Kim & A Marshall (eds), Proceedings - IEEE International SOC Conference, 2005 SOCC., P.6, Proceedings - IEEE International SOC Conference, pp. 87-88, 2005 IEEE International SOC Conference, Herndon, VA, United States, 09/25/05.

Design study of (2 × 2) core architecture for matrix multiplications via Programmable Graph Architecture. / Mun, Jun Hee; Peng, Muling; Hong, Sangjin et al.
Proceedings - IEEE International SOC Conference, 2005 SOCC. ed. / D. Ha; R. Krishnamurthy; S. Kim; A. Marshall. 2005. p. 87-88 P.6 (Proceedings - IEEE International SOC Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design study of (2 × 2) core architecture for matrix multiplications via Programmable Graph Architecture

AU - Mun, Jun Hee

AU - Peng, Muling

AU - Hong, Sangjin

AU - Doboli, Alex

AU - Tang, K. Wendy

PY - 2005

Y1 - 2005

N2 - This paper presents a 2 × 2 core architecture for matrix multiplications via the Programmable Graph Architecture approach proposed earlier. A larger matrix-matrix multiplication can be carried out through sub-matrix decomposition. The iterative operation is completely performed with simple arithmetic operations and memory accesses. The core architecture is structurally described using Verilog and its functionality has been verified. Performance of the operation and factors influencing the execution are analyzed.

AB - This paper presents a 2 × 2 core architecture for matrix multiplications via the Programmable Graph Architecture approach proposed earlier. A larger matrix-matrix multiplication can be carried out through sub-matrix decomposition. The iterative operation is completely performed with simple arithmetic operations and memory accesses. The core architecture is structurally described using Verilog and its functionality has been verified. Performance of the operation and factors influencing the execution are analyzed.

UR - https://www.scopus.com/pages/publications/30844455577

M3 - Conference contribution

SN - 0780392647

SN - 9780780392649

T3 - Proceedings - IEEE International SOC Conference

SP - 87

EP - 88

BT - Proceedings - IEEE International SOC Conference, 2005 SOCC

A2 - Ha, D.

A2 - Krishnamurthy, R.

A2 - Kim, S.

A2 - Marshall, A.

T2 - 2005 IEEE International SOC Conference

Y2 - 25 September 2005 through 28 September 2005

ER -

Design study of (2 × 2) core architecture for matrix multiplications via Programmable Graph Architecture

Abstract

Publication series

Conference

Other files and links

Fingerprint

Cite this