Development of a numerical model for non-uniformly powered die to improve both thermal and device clock performance

Integration of different functional components such as level two (L2) cache memory, high-speed I/O interfaces, memory controller, etc. has enhanced microprocessor performance. In this architecture, certain functional units on the microprocessor dissipate a significant fraction of the total power while other functional blocks dissipate little or no power. This highly non-uniform power distribution results in a large temperature gradient with localized hot spots that may have detrimental effect on computer performance and product reliability as well as yield. Moving the functional blocks may reduce the junction temperature but can also affect the performance by a factor as high as 35%. In this paper, multi-objective optimization is performed to minimize the junction temperature without significantly altering the computer performance. From the results, the minimum and the maximum temperature was 82.4°C and 94.5°C with a corresponding penalty on the performance of 35% and 0% respectively. The optimized location of the functional blocks resulted in a temperature of 83.2°C for a performance loss of 5%.