TY - GEN
T1 - Development of low power DAC with pseudo Fibonacci sequence
AU - Kubokawa, Ryota
AU - Ohshima, Takashi
AU - Tomar, Abhishek
AU - Ramesh, Pokharel
AU - Kanaya, Haruichi
AU - Yoshida, Keiji
PY - 2010
Y1 - 2010
N2 - A 12-bit Digital-analog converter (DAC) with pseudo Fibonacci sequence was fabricated in a 0.18μm CMOS technology. Proposed 12-bit DAC is composed of a 6-bit pseudo Fibonacci sequence and 6bit unary sequence. The power consumption of the proposed DAC is expected lower than that of conventional binary and unary DAC. The simulated power consumption of proposed 12-bit DAC is 40mV at 3.3V supply voltage. Also we fabricated the prototype 6-bit DAC with pseudo Fibonacci sequence and tested. The measured power consumption is very low and almost the same value as a simulated value.
AB - A 12-bit Digital-analog converter (DAC) with pseudo Fibonacci sequence was fabricated in a 0.18μm CMOS technology. Proposed 12-bit DAC is composed of a 6-bit pseudo Fibonacci sequence and 6bit unary sequence. The power consumption of the proposed DAC is expected lower than that of conventional binary and unary DAC. The simulated power consumption of proposed 12-bit DAC is 40mV at 3.3V supply voltage. Also we fabricated the prototype 6-bit DAC with pseudo Fibonacci sequence and tested. The measured power consumption is very low and almost the same value as a simulated value.
KW - Digital-analog converter (DAC)
KW - low-power consumption
KW - pseudo Fibonacci sequence
UR - https://www.scopus.com/pages/publications/79959255838
U2 - 10.1109/APCCAS.2010.5774936
DO - 10.1109/APCCAS.2010.5774936
M3 - Conference contribution
SN - 9781424474561
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 370
EP - 373
BT - Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
T2 - 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Y2 - 6 December 2010 through 9 December 2010
ER -