Die stress analysis in Stacked Die Chip Scale Packages (SCSP)

As board real estate becomes more precious and market demand for increased functional density in modules rises, engineers are looking at 3-dimensional packaging to provide the solutions. Stacked die technology, which involves stacking the die one above another, is fast becoming the preferred packaging option for memory applications in handheld consumer products where board space is a premium. The current study focuses on the stacked die wire bonded CSP (SCSP). The CSP offers reduced package size while the vertical stacking provides a smaller form for multi-chip integration compared to a horizontal layout. In some test chip designs, it has been observed that passivation cracks occur on the functional surface of the top die as a result of thermal cycling. Stress analysis using the finite element method has been carried out to understand the effect of package parameters on die stress under cycling conditions. The distribution of the stress components that may cause this passivation cracking are discussed. The stress magnitudes observed in the SCSP are compared with those of a single die package where no passivation cracks have been observed to obtain a quantitative perspective of the stress. Results reported for parametric studies include the effect of variation of die thickness, spacer size and thickness, and thickness of overmold compound above the die. Finally, design considerations for two-die, over-molded, wire-bond, stacked die packages are presented based on the above study.