@inproceedings{9de604c3f5dc4775b883e86931029737,
title = "EA-PLRU: Enclave-aware cache replacement",
abstract = "In SGX-based systems, cache lines belonging to enclaves must be encrypted when they are evicted from the last-level cache, and decrypted on a cache miss before they are brought into the cache from memory. Because encryption and decryption introduce overheads in terms of performance, memory pressure and power consumption, it is important to reduce the frequency of LLC misses and replacements of enclave lines. We consider a system where enclave and non-enclave applications co-exist in the system and share the last-level cache. To decrease the frequency of encrypt/decrypt operations, we introduce a new cache replacement policy that slightly favors enclave lines over non-enclave lines. Specifically, we modify the last level of pseudo-LRU replacement logic, so that it favors an enclave line over a non-enclave line regardless of how recently each line has been accessed. We also add a probabilistic component to this new policy to balance performance and make replacement policy non-deterministic and therefore resilient to side-channel attacks that exploit predictable patterns of cache line replacement.",
keywords = "Cache, Cache replacement, Ea-plru, Enclave, Intel sgx, Plru",
author = "Atsuko Shimizu and Daniel Townley and Mohit Joshi and Dmitry Ponomarev",
note = "Publisher Copyright: {\textcopyright} 2019 Association for Computing Machinery.; 8th International Workshop on Hardware and Architectural Support for Security and Privacy, HASP 2019 ; Conference date: 23-06-2019",
year = "2019",
month = jun,
day = "23",
doi = "10.1145/3337167.3337172",
language = "English",
series = "ACM International Conference Proceeding Series",
publisher = "Association for Computing Machinery",
booktitle = "Proceedings of the 8th International Workshop on Hardware and Architectural Support for Security and Privacy, HASP 2019",
}