TY - GEN
T1 - Enabling future generation high-speed inspection through a massively parallel e-beam approach
AU - Malloy, Matt
AU - Bunday, Benjamin
AU - Wurm, Stefan
AU - Thiel, Brad
AU - Kemen, Thomas
AU - Zeidler, Dirk
AU - Eberle, Anna Lena
AU - Garbowski, Tomasz
AU - Dellemann, Gregor
AU - Peters, Jan Hendrik
N1 - Publisher Copyright: © 2015 IEEE.
PY - 2015/7/22
Y1 - 2015/7/22
N2 - New device architectures and materials are being introduced to develop 10 and 7 nm node manufacturing processes. In addition, the increasing complexity of multiple patterning adds significant yield challenges. The critical metrology challenges for yield assurance include defect control, control of critical dimension and critical dimension uniformity, and pattern placement control. To support the industry in meeting those challenges SEMATECH continues to evaluate new disruptive metrology technologies that can meet the requirements for high volume manufacturing (HVM). High-speed massively parallel e-beam defect inspection has the potential to address the key gaps limiting today's patterned defect inspection in the fab; primarily, throughput and sensitivity to detect ultra-small critical defects. While SEMATECH targets patterned defect inspection first, the technology also has the potential to support the increasing number of hot spot inspection requirements related to critical dimension uniformity and pattern placement that come with self-Aligned quadruple patterning. In addition to wafer applications, next generation mask inspection will benefit from a faster high resolution inspection technology. In late 2014 SEMATECH completed a review, system analysis, and proof of concept evaluation of multiple e-beam technologies for patterned wafer inspection. The selection of a champion technology was made and a core technology maturation phase started with the goal of enabling the eventual commercialization of an HVM system. This paper begins with a brief overview of the industry need and the program being developed to address it. Key technical topics pertaining to imaging performance and defect sensitivity are then examined. Performance data from early proof of concept systems will be shown. The capabilities in development to accurately access defect sensitivity using the core technology will be discussed, and initial results for two types of samples will be provided. Development towards the next generation of non-proprietary test samples will also be presented.
AB - New device architectures and materials are being introduced to develop 10 and 7 nm node manufacturing processes. In addition, the increasing complexity of multiple patterning adds significant yield challenges. The critical metrology challenges for yield assurance include defect control, control of critical dimension and critical dimension uniformity, and pattern placement control. To support the industry in meeting those challenges SEMATECH continues to evaluate new disruptive metrology technologies that can meet the requirements for high volume manufacturing (HVM). High-speed massively parallel e-beam defect inspection has the potential to address the key gaps limiting today's patterned defect inspection in the fab; primarily, throughput and sensitivity to detect ultra-small critical defects. While SEMATECH targets patterned defect inspection first, the technology also has the potential to support the increasing number of hot spot inspection requirements related to critical dimension uniformity and pattern placement that come with self-Aligned quadruple patterning. In addition to wafer applications, next generation mask inspection will benefit from a faster high resolution inspection technology. In late 2014 SEMATECH completed a review, system analysis, and proof of concept evaluation of multiple e-beam technologies for patterned wafer inspection. The selection of a champion technology was made and a core technology maturation phase started with the goal of enabling the eventual commercialization of an HVM system. This paper begins with a brief overview of the industry need and the program being developed to address it. Key technical topics pertaining to imaging performance and defect sensitivity are then examined. Performance data from early proof of concept systems will be shown. The capabilities in development to accurately access defect sensitivity using the core technology will be discussed, and initial results for two types of samples will be provided. Development towards the next generation of non-proprietary test samples will also be presented.
UR - https://www.scopus.com/pages/publications/84963649636
U2 - 10.1109/ASMC.2015.7164492
DO - 10.1109/ASMC.2015.7164492
M3 - Conference contribution
T3 - 2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2015
SP - 266
EP - 271
BT - 2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 26th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2015
Y2 - 3 May 2015 through 6 May 2015
ER -