Abstract
Signal processing algorithms represented by data flow graphs can be efficiently mapped to hardware usign a block level pipelining architecture. In this scheme, nodes of data flow are mapped to processing blocks and buffers are inserted in between as pipelining elements. We present in this paper a methodology for equalizing execution times of various nodes in the data path. The method is used to minimize the power dissipation and buffer usage by judiciously selecting the execution speed of hardware units. The block level pipelining allows for simple local controllers for each buffer which are generated by the global controller based on data flow specifications. The evaluation of the methodology on a practical example is presented.
| Original language | English |
|---|---|
| Article number | 1464920 |
| Pages (from-to) | 1646-1649 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| DOIs | |
| State | Published - 2005 |
| Event | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: May 23 2005 → May 26 2005 |
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