Fermi-level pinning at the polysilicon/metal-oxide interface - Part II

Christopher C. Hobbs; Leonardo R.C. Fonseca; Andrey Knizhnik; Veeraraghavan Dhandapani; Srikanth B. Samavedam; William J. Taylor; John M. Grant; Lu Rae G. Dip; Dina H. Triyoso; Rama I. Hegde; David C. Gilmer; Ricardo Garcia; Darrell Roan; M. Luke Lovejoy; Raghaw S. Rai; Elizabeth A. Hebert; Hsing Huang Tseng; Steven G.H. Anderson; Bruce E. White; Philip J. Tobin

doi:10.1109/TED.2004.829510

Fermi-level pinning at the polysilicon/metal-oxide interface - Part II

Christopher C. Hobbs
, Leonardo R.C. Fonseca
, Andrey Knizhnik
, Veeraraghavan Dhandapani
, Srikanth B. Samavedam
, William J. Taylor
, John M. Grant
, Lu Rae G. Dip
, Dina H. Triyoso
, Rama I. Hegde
, David C. Gilmer
, Ricardo Garcia
, Darrell Roan
, M. Luke Lovejoy
, Raghaw S. Rai
, Elizabeth A. Hebert
, Hsing Huang Tseng
, Steven G.H. Anderson
, Bruce E. White
, Philip J. Tobin

Physics

Binghamton University

Motorola
Kintech Lab Ltd
NanoCoolers

Research output: Contribution to journal › Article › peer-review

123 Scopus citations

Abstract

We report here that Fermi pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices. In Part I, we investigated the different gatestack regions and determined that the polysilicon/metal oxide interface plays a key role on the threshold voltages. Now in Part II, the effects of the interfacial bonding are examined by experiments with submonolayer atomic-layer deposition (ALD) metal oxides and atomistic simulation. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO₂ and Al₂O₃, respectively. Oxygen vacancies at polysilicon/HfO₂ interfaces also lead to Fermi pinning. This fundamental characteristic affects the observed polysilicon depletion.

Original language	English
Pages (from-to)	978-984
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	51
Issue number	6
DOIs	https://doi.org/10.1109/TED.2004.829510
State	Published - Jun 2004

Keywords

AlO
Fermi pinning
Gate dielectric
HfO
Polysilicon

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10.1109/TED.2004.829510

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Hobbs, C. C., Fonseca, L. R. C., Knizhnik, A., Dhandapani, V., Samavedam, S. B., Taylor, W. J., Grant, J. M., Dip, L. R. G., Triyoso, D. H., Hegde, R. I., Gilmer, D. C., Garcia, R., Roan, D., Lovejoy, M. L., Rai, R. S., Hebert, E. A., Tseng, H. H., Anderson, S. G. H., White, B. E., & Tobin, P. J. (2004). Fermi-level pinning at the polysilicon/metal-oxide interface - Part II. IEEE Transactions on Electron Devices, 51(6), 978-984. https://doi.org/10.1109/TED.2004.829510

@article{79475b0be27b46a2845ef8ed89a74a0a,

title = "Fermi-level pinning at the polysilicon/metal-oxide interface - Part II",

abstract = "We report here that Fermi pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices. In Part I, we investigated the different gatestack regions and determined that the polysilicon/metal oxide interface plays a key role on the threshold voltages. Now in Part II, the effects of the interfacial bonding are examined by experiments with submonolayer atomic-layer deposition (ALD) metal oxides and atomistic simulation. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO2 and Al2O3, respectively. Oxygen vacancies at polysilicon/HfO2 interfaces also lead to Fermi pinning. This fundamental characteristic affects the observed polysilicon depletion.",

keywords = "AlO, Fermi pinning, Gate dielectric, HfO, Polysilicon",

author = "Hobbs, \{Christopher C.\} and Fonseca, \{Leonardo R.C.\} and Andrey Knizhnik and Veeraraghavan Dhandapani and Samavedam, \{Srikanth B.\} and Taylor, \{William J.\} and Grant, \{John M.\} and Dip, \{Lu Rae G.\} and Triyoso, \{Dina H.\} and Hegde, \{Rama I.\} and Gilmer, \{David C.\} and Ricardo Garcia and Darrell Roan and Lovejoy, \{M. Luke\} and Rai, \{Raghaw S.\} and Hebert, \{Elizabeth A.\} and Tseng, \{Hsing Huang\} and Anderson, \{Steven G.H.\} and White, \{Bruce E.\} and Tobin, \{Philip J.\}",

year = "2004",

month = jun,

doi = "10.1109/TED.2004.829510",

language = "English",

volume = "51",

pages = "978--984",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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}

Hobbs, CC, Fonseca, LRC, Knizhnik, A, Dhandapani, V, Samavedam, SB, Taylor, WJ, Grant, JM, Dip, LRG, Triyoso, DH, Hegde, RI, Gilmer, DC, Garcia, R, Roan, D, Lovejoy, ML, Rai, RS, Hebert, EA, Tseng, HH, Anderson, SGH, White, BE & Tobin, PJ 2004, 'Fermi-level pinning at the polysilicon/metal-oxide interface - Part II', IEEE Transactions on Electron Devices, vol. 51, no. 6, pp. 978-984. https://doi.org/10.1109/TED.2004.829510

TY - JOUR

T1 - Fermi-level pinning at the polysilicon/metal-oxide interface - Part II

AU - Hobbs, Christopher C.

AU - Fonseca, Leonardo R.C.

AU - Knizhnik, Andrey

AU - Dhandapani, Veeraraghavan

AU - Samavedam, Srikanth B.

AU - Taylor, William J.

AU - Grant, John M.

AU - Dip, Lu Rae G.

AU - Triyoso, Dina H.

AU - Hegde, Rama I.

AU - Gilmer, David C.

AU - Garcia, Ricardo

AU - Roan, Darrell

AU - Lovejoy, M. Luke

AU - Rai, Raghaw S.

AU - Hebert, Elizabeth A.

AU - Tseng, Hsing Huang

AU - Anderson, Steven G.H.

AU - White, Bruce E.

AU - Tobin, Philip J.

PY - 2004/6

Y1 - 2004/6

N2 - We report here that Fermi pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices. In Part I, we investigated the different gatestack regions and determined that the polysilicon/metal oxide interface plays a key role on the threshold voltages. Now in Part II, the effects of the interfacial bonding are examined by experiments with submonolayer atomic-layer deposition (ALD) metal oxides and atomistic simulation. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO2 and Al2O3, respectively. Oxygen vacancies at polysilicon/HfO2 interfaces also lead to Fermi pinning. This fundamental characteristic affects the observed polysilicon depletion.

AB - We report here that Fermi pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices. In Part I, we investigated the different gatestack regions and determined that the polysilicon/metal oxide interface plays a key role on the threshold voltages. Now in Part II, the effects of the interfacial bonding are examined by experiments with submonolayer atomic-layer deposition (ALD) metal oxides and atomistic simulation. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO2 and Al2O3, respectively. Oxygen vacancies at polysilicon/HfO2 interfaces also lead to Fermi pinning. This fundamental characteristic affects the observed polysilicon depletion.

KW - AlO

KW - Fermi pinning

KW - Gate dielectric

KW - HfO

KW - Polysilicon

UR - https://www.scopus.com/pages/publications/2942657401

U2 - 10.1109/TED.2004.829510

DO - 10.1109/TED.2004.829510

M3 - Article

SN - 0018-9383

VL - 51

SP - 978

EP - 984

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 6

ER -

Fermi-level pinning at the polysilicon/metal-oxide interface - Part II

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Keywords

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