FFT compiler: From math to efficient hardware

Peter A. Milder; Franz Franchetti; James C. Hoe; Markus Püschel

doi:10.1109/HLDVT.2007.4392801

FFT compiler: From math to efficient hardware

Peter A. Milder
, Franz Franchetti
, James C. Hoe
, Markus Püschel

Electrical Engineering

Stony Brook University

Carnegie Mellon University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper presents a high-level compiler that generates hardware implementations of the discrete Fourier transform (DFT) from mathematical specifications. The matrix formula input language captures not only the DFT calculation but also the implementation options at the algorithmic and architectural levels. By selecting the appropriate formula, the resulting hardware implementations (described in a synthesizable Verilog description) can achieve a wide range of tradeoffs between implementation cost and performance. The compiler is also parameterized for a set of technology-specific optimizations, to allow it to target specific implementation platforms. This paper gives a brief overview of the system and presents synthesis results.

Original language	English
Title of host publication	Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT
Pages	137-139
Number of pages	3
DOIs	https://doi.org/10.1109/HLDVT.2007.4392801
State	Published - 2007
Event	IEEE International High-Level Design Validation and Test Workshop, HLDVT - Irvine, CA, United States Duration: Nov 7 2007 → Nov 9 2007

Publication series

Name	Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Conference

Conference	IEEE International High-Level Design Validation and Test Workshop, HLDVT
Country/Territory	United States
City	Irvine, CA
Period	11/7/07 → 11/9/07

Access to Document

10.1109/HLDVT.2007.4392801

Cite this

@inproceedings{a74d0ba8bffc4d7e8ad821fc03838303,

title = "FFT compiler: From math to efficient hardware",

abstract = "This paper presents a high-level compiler that generates hardware implementations of the discrete Fourier transform (DFT) from mathematical specifications. The matrix formula input language captures not only the DFT calculation but also the implementation options at the algorithmic and architectural levels. By selecting the appropriate formula, the resulting hardware implementations (described in a synthesizable Verilog description) can achieve a wide range of tradeoffs between implementation cost and performance. The compiler is also parameterized for a set of technology-specific optimizations, to allow it to target specific implementation platforms. This paper gives a brief overview of the system and presents synthesis results.",

author = "Milder, \{Peter A.\} and Franz Franchetti and Hoe, \{James C.\} and Markus P{\"u}schel",

year = "2007",

doi = "10.1109/HLDVT.2007.4392801",

language = "English",

isbn = "1424414806",

series = "Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT",

pages = "137--139",

booktitle = "Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT",

note = "IEEE International High-Level Design Validation and Test Workshop, HLDVT ; Conference date: 07-11-2007 Through 09-11-2007",

}

Milder, PA, Franchetti, F, Hoe, JC & Püschel, M 2007, FFT compiler: From math to efficient hardware. in Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT., 4392801, Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT, pp. 137-139, IEEE International High-Level Design Validation and Test Workshop, HLDVT, Irvine, CA, United States, 11/7/07. https://doi.org/10.1109/HLDVT.2007.4392801

FFT compiler: From math to efficient hardware. / Milder, Peter A.; Franchetti, Franz; Hoe, James C. et al.
Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT. 2007. p. 137-139 4392801 (Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - FFT compiler

T2 - IEEE International High-Level Design Validation and Test Workshop, HLDVT

AU - Milder, Peter A.

AU - Franchetti, Franz

AU - Hoe, James C.

AU - Püschel, Markus

PY - 2007

Y1 - 2007

N2 - This paper presents a high-level compiler that generates hardware implementations of the discrete Fourier transform (DFT) from mathematical specifications. The matrix formula input language captures not only the DFT calculation but also the implementation options at the algorithmic and architectural levels. By selecting the appropriate formula, the resulting hardware implementations (described in a synthesizable Verilog description) can achieve a wide range of tradeoffs between implementation cost and performance. The compiler is also parameterized for a set of technology-specific optimizations, to allow it to target specific implementation platforms. This paper gives a brief overview of the system and presents synthesis results.

AB - This paper presents a high-level compiler that generates hardware implementations of the discrete Fourier transform (DFT) from mathematical specifications. The matrix formula input language captures not only the DFT calculation but also the implementation options at the algorithmic and architectural levels. By selecting the appropriate formula, the resulting hardware implementations (described in a synthesizable Verilog description) can achieve a wide range of tradeoffs between implementation cost and performance. The compiler is also parameterized for a set of technology-specific optimizations, to allow it to target specific implementation platforms. This paper gives a brief overview of the system and presents synthesis results.

UR - https://www.scopus.com/pages/publications/47949124194

U2 - 10.1109/HLDVT.2007.4392801

DO - 10.1109/HLDVT.2007.4392801

M3 - Conference contribution

SN - 1424414806

SN - 9781424414802

T3 - Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

SP - 137

EP - 139

BT - Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Y2 - 7 November 2007 through 9 November 2007

ER -

FFT compiler: From math to efficient hardware

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this