Glitching power reduction through supply voltage adaptation mechanism for low power array structure design

Sangjin Hong; Shu Shin Chin; Magesh Sadasivam

Glitching power reduction through supply voltage adaptation mechanism for low power array structure design

Sangjin Hong
, Shu Shin Chin
, Magesh Sadasivam

Electrical Engineering

Stony Brook University

Stony Brook University

Research output: Contribution to journal › Conference article › peer-review

Abstract

A novel supply voltage switching mechanism for reducing power dissipation of array structures is presented. With this mechanism, the supply voltage levels are successively activated by external clock signal in the direction of signal propagation. The mechanism eliminates power dissipated by the glitches while the speed of the array structure can be maintained. The mechanism is easily incorporated so that no circuit change in the existing array structure is required.

Original language	English
Pages (from-to)	II733-II736
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
State	Published - 2004
Event	2004 IEEE International Symposium on Circuits and Systems - Proceedings - Vancouver, BC, Canada Duration: May 23 2004 → May 26 2004

Cite this

@article{5fbe4fe2e5e14ebe9d92ca61f1a58702,

title = "Glitching power reduction through supply voltage adaptation mechanism for low power array structure design",

abstract = "A novel supply voltage switching mechanism for reducing power dissipation of array structures is presented. With this mechanism, the supply voltage levels are successively activated by external clock signal in the direction of signal propagation. The mechanism eliminates power dissipated by the glitches while the speed of the array structure can be maintained. The mechanism is easily incorporated so that no circuit change in the existing array structure is required.",

author = "Sangjin Hong and Chin, \{Shu Shin\} and Magesh Sadasivam",

year = "2004",

language = "English",

volume = "2",

pages = "II733--II736",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2004 IEEE International Symposium on Circuits and Systems - Proceedings ; Conference date: 23-05-2004 Through 26-05-2004",

}

TY - JOUR

T1 - Glitching power reduction through supply voltage adaptation mechanism for low power array structure design

AU - Hong, Sangjin

AU - Chin, Shu Shin

AU - Sadasivam, Magesh

PY - 2004

Y1 - 2004

N2 - A novel supply voltage switching mechanism for reducing power dissipation of array structures is presented. With this mechanism, the supply voltage levels are successively activated by external clock signal in the direction of signal propagation. The mechanism eliminates power dissipated by the glitches while the speed of the array structure can be maintained. The mechanism is easily incorporated so that no circuit change in the existing array structure is required.

AB - A novel supply voltage switching mechanism for reducing power dissipation of array structures is presented. With this mechanism, the supply voltage levels are successively activated by external clock signal in the direction of signal propagation. The mechanism eliminates power dissipated by the glitches while the speed of the array structure can be maintained. The mechanism is easily incorporated so that no circuit change in the existing array structure is required.

UR - https://www.scopus.com/pages/publications/4344641519

M3 - Conference article

SN - 0271-4310

VL - 2

SP - II733-II736

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2004 IEEE International Symposium on Circuits and Systems - Proceedings

Y2 - 23 May 2004 through 26 May 2004

ER -

Glitching power reduction through supply voltage adaptation mechanism for low power array structure design

Abstract

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