HLL ARCHITECTURE FOR AN AREA-EFFICIENT MULTI-CHIP VLSI IMPLEMENTATION.

The emergence of Reduced Instruction Set Computers (RISCs) has clearly demonstrated the advantages of using VLSI chip area in a effective way. While the usefulness of a language-directed architecture in reducing the semantic gap and its associated problems is well known, technological limitations forbid their single-chip implementation with the same advantages as the RISCs. We present a High Level Language (HLL) architecture that employs capability-based addressing, tags and descriptors to provide a high degree of support for programming languages and operating systems. We then propose a technique for a multi-chip implementation of this HLL architecture that uses RISC-like components. The apparent interprocessor communication overhead in the system is masked by the high-level semantics of the co-processor-executed instructions and the ability to cache significant amount of data on each chip.