Implementing degradable processing arrays

Stephanie R. Goldberg; Shambhu J. Upadhyaya

doi:10.1109/40.653036

Implementing degradable processing arrays

Stephanie R. Goldberg
, Shambhu J. Upadhyaya

Department of Computer Science and Engineering

University at Buffalo

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

A commercially feasible multichip module-based faulttolerance scheme incurs no increase to primary circuit area.

Original language	English
Pages (from-to)	64-74
Number of pages	11
Journal	IEEE Micro
Volume	18
Issue number	1
DOIs	https://doi.org/10.1109/40.653036
State	Published - Jan 1998

Access to Document

10.1109/40.653036

Cite this

@article{52712113890e4819a8b916f1e764430e,

title = "Implementing degradable processing arrays",

abstract = "A commercially feasible multichip module-based faulttolerance scheme incurs no increase to primary circuit area.",

author = "Goldberg, \{Stephanie R.\} and Upadhyaya, \{Shambhu J.\}",

year = "1998",

month = jan,

doi = "10.1109/40.653036",

language = "English",

volume = "18",

pages = "64--74",

journal = "IEEE Micro",

issn = "0272-1732",

publisher = "IEEE Computer Society",

number = "1",

}

TY - JOUR

T1 - Implementing degradable processing arrays

AU - Goldberg, Stephanie R.

AU - Upadhyaya, Shambhu J.

PY - 1998/1

Y1 - 1998/1

N2 - A commercially feasible multichip module-based faulttolerance scheme incurs no increase to primary circuit area.

AB - A commercially feasible multichip module-based faulttolerance scheme incurs no increase to primary circuit area.

UR - https://www.scopus.com/pages/publications/0031649980

U2 - 10.1109/40.653036

DO - 10.1109/40.653036

M3 - Article

SN - 0272-1732

VL - 18

SP - 64

EP - 74

JO - IEEE Micro

JF - IEEE Micro

IS - 1

ER -

Implementing degradable processing arrays

Abstract

Access to Document

Other files and links

Fingerprint

Cite this