Input controlled refresh for noise tolerant dynamic circuits

The increasing impact of noise in deep submicron designs combined with a need for high performance circuits warrants development of noise tolerant dynamic circuits. A circuit technique for addressing this problem is presented in this paper. Traditionally, an output controlled refresh has been used for providing noise immunity to the dynamic node. An input controlled refresh technique has been developed for noise-free performance with minimal impact on delay and power. Also this technique eliminates functional failure that occurs due to charge loss from the dynamic node. A metric, Unity Noise Gain (UNG) has been used to compare the proposed method with the existing approaches. Simulations show a significant improvement is noise immunity, for a NAND gate and an adder circuit.