Integrated Chip-Scale Prediction of Copper Interconnect Topography

In this work, we present an integrated prediction of thickness variations in electroplating and chemical mechanical polishing (CMP) processes across an entire chip for random layouts. We achieve chip-scale prediction by first calibrating both electroplating and CMP models with experimental data using the same test mask. Using the calibrated plating model in conjunction with a discretized and binned layout extraction for a random chip layout, a prediction of plated copper topography is then performed. Finally, using the plated thickness prediction as the initial condition, the CMP model predicts the dishing and erosion across the chip. Layout geometry extraction for each discretized region of a chip as well as layout parameter manipulation and model output integration are all critical elements, in addition to the model development itself, enabling the integrated chip-scale prediction of final copper interconnect thickness variation.