Integration of ICP high-density plasma CVD with CMP and its effects on planarity for sub-0.5-um CMOS technology

The planarity and gap-fill requirements for interlevel dielectrics become increasingly stringent as design rules shrink below 0.5 μm. In this study, we investigated the resulting gap-fill and planarity (both before and after CMP) for an interlevel dielectric stack consisting of inductively coupled high density plasma (HDP) CVD oxide and a standard PECVD SiH₄ oxide. Results show that the etch- to-deposition ratio and the thickness of the HDP CVD oxide will influence the final topography (both profiles and step height) before CMP. An optimum HDP oxide thickness was identified in order to achieve void-free deposition of the PECVD SiH₄ oxide, minimize time to planarize, and maximize tool throughputs for HDP and CMP. It was also seen that the resulting planarity after CMP is significantly dependent upon the underlying feature and feature dimension. This paper provides information on the integration of HDP CVD oxide with CMP For a sub-0.5 μm CMOS technology, and on the optimum HDP CVD oxide deposition conditions and thickness necessary to achieve a cost-effective, production- worthy process.