TY - GEN
T1 - Layout conscious bus architecture synthesis for deep submicron systems on chip
AU - Thepayasuwan, Nattawut
AU - Doboli, Alex
PY - 2004
Y1 - 2004
N2 - System-level design has a disadvantage in not knowing important aspects about the final layout. This is critical for SoC, where uncertainties in communication delay by very deep submicron effects cannot be neglected. This paper presents a layout-aware bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. BA synthesis includes finding bus topology and routing individual buses, so that constraints like area, bus speed and length, are tackled at the physical level. The paper presents the BA automatically synthesized for a network processor and a JPEG SoC.
AB - System-level design has a disadvantage in not knowing important aspects about the final layout. This is critical for SoC, where uncertainties in communication delay by very deep submicron effects cannot be neglected. This paper presents a layout-aware bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. BA synthesis includes finding bus topology and routing individual buses, so that constraints like area, bus speed and length, are tackled at the physical level. The paper presents the BA automatically synthesized for a network processor and a JPEG SoC.
UR - https://www.scopus.com/pages/publications/3042515561
U2 - 10.1109/DATE.2004.1268835
DO - 10.1109/DATE.2004.1268835
M3 - Conference contribution
SN - 0769520855
SN - 9780769520858
T3 - Proceedings - Design, Automation and Test in Europe Conference and Exhibition
SP - 108
EP - 113
BT - Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
A2 - Gielen, G.
A2 - Figueras, J.
T2 - Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
Y2 - 16 February 2004 through 20 February 2004
ER -