Low-power turbo equalizer architecture

Seok Jun Lee; N. R. Shanbhag; A. C. Singer

doi:10.1109/SIPS.2002.1049681

Low-power turbo equalizer architecture

Seok Jun Lee
, N. R. Shanbhag
, A. C. Singer

Office of the Dean of the College of Engineering and Applied Sciences

Stony Brook University

University of Illinois at Urbana-Champaign

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

7 Scopus citations

Abstract

In this paper, we propose a low complexity architecture for turbo equalizers. Turbo equalizers jointly equalize and decode the received signal by exchanging soft information iteratively. The proposed architecture employs early termination of the iterative process when it does not impact the bit-error rate (BER). Early termination enables the powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power. Simulation results show that the complexity is reduced by 20% ∼ 59% and 8% ∼ 58% in equalization and decoding, respectively. In addition, the number of iterations is reduced by 30% ∼ 47% with negligible degradation in BER.

Original language	English
Title of host publication	IEEE Workshop on Signal Processing Systems, SiPS
Subtitle of host publication	Design and Implementation
Pages	33-38
Number of pages	6
ISBN (Electronic)	0780375874
DOIs	https://doi.org/10.1109/SIPS.2002.1049681
State	Published - 2002

Keywords

Binary phase shift keying
Bit error rate
DSL
Decision feedback equalizers
Degradation
Design optimization
Frequency
Intersymbol interference
Iterative decoding
Termination of employment

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10.1109/SIPS.2002.1049681

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title = "Low-power turbo equalizer architecture",

abstract = "In this paper, we propose a low complexity architecture for turbo equalizers. Turbo equalizers jointly equalize and decode the received signal by exchanging soft information iteratively. The proposed architecture employs early termination of the iterative process when it does not impact the bit-error rate (BER). Early termination enables the powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power. Simulation results show that the complexity is reduced by 20\% ∼ 59\% and 8\% ∼ 58\% in equalization and decoding, respectively. In addition, the number of iterations is reduced by 30\% ∼ 47\% with negligible degradation in BER.",

keywords = "Binary phase shift keying, Bit error rate, DSL, Decision feedback equalizers, Degradation, Design optimization, Frequency, Intersymbol interference, Iterative decoding, Termination of employment",

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AB - In this paper, we propose a low complexity architecture for turbo equalizers. Turbo equalizers jointly equalize and decode the received signal by exchanging soft information iteratively. The proposed architecture employs early termination of the iterative process when it does not impact the bit-error rate (BER). Early termination enables the powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power. Simulation results show that the complexity is reduced by 20% ∼ 59% and 8% ∼ 58% in equalization and decoding, respectively. In addition, the number of iterations is reduced by 30% ∼ 47% with negligible degradation in BER.

KW - Binary phase shift keying

KW - Bit error rate

KW - DSL

KW - Decision feedback equalizers

KW - Degradation

KW - Design optimization

KW - Frequency

KW - Intersymbol interference

KW - Iterative decoding

KW - Termination of employment

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DO - 10.1109/SIPS.2002.1049681

M3 - Chapter

SP - 33

EP - 38

BT - IEEE Workshop on Signal Processing Systems, SiPS

ER -

Low-power turbo equalizer architecture

Abstract

Keywords

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