Making address-correlated prefetching practical

Thomas F. Wenisch; Michael Ferdman; Anastasia Ailamaki; Babak Falsafi; Andreas Moshovos

doi:10.1109/MM.2010.21

Making address-correlated prefetching practical

Thomas F. Wenisch
, Michael Ferdman
, Anastasia Ailamaki
, Babak Falsafi
, Andreas Moshovos

Computer Science

Stony Brook University

University of Michigan, Ann Arbor
Swiss Federal Institute of Technology Lausanne
University of Toronto

Research output: Contribution to journal › Article › peer-review

19 Scopus citations

Abstract

Despite a decade of research demonstrating its efficacy, address-correlated prefetching has never been implemented in a shipping processor because it requires megabytes of metadata - too large to store practically on chip. New storage-, latency-, and bandwidth-efficient mechanisms for storing metadata off chip yield a practical design that achieves 90 percent of the performance potential of idealized on-chip metadata storage.

Original language	English
Article number	5430739
Pages (from-to)	50-59
Number of pages	10
Journal	IEEE Micro
Volume	30
Issue number	1
DOIs	https://doi.org/10.1109/MM.2010.21
State	Published - Jan 2010

Keywords

Address-correlated prefetching
Cache memories

Access to Document

10.1109/MM.2010.21

Cite this

@article{a6e9930aa24b48c4b10718d5563df9fb,

title = "Making address-correlated prefetching practical",

abstract = "Despite a decade of research demonstrating its efficacy, address-correlated prefetching has never been implemented in a shipping processor because it requires megabytes of metadata - too large to store practically on chip. New storage-, latency-, and bandwidth-efficient mechanisms for storing metadata off chip yield a practical design that achieves 90 percent of the performance potential of idealized on-chip metadata storage.",

keywords = "Address-correlated prefetching, Cache memories",

author = "Wenisch, \{Thomas F.\} and Michael Ferdman and Anastasia Ailamaki and Babak Falsafi and Andreas Moshovos",

year = "2010",

month = jan,

doi = "10.1109/MM.2010.21",

language = "English",

volume = "30",

pages = "50--59",

journal = "IEEE Micro",

issn = "0272-1732",

publisher = "IEEE Computer Society",

number = "1",

}

TY - JOUR

T1 - Making address-correlated prefetching practical

AU - Wenisch, Thomas F.

AU - Ferdman, Michael

AU - Ailamaki, Anastasia

AU - Falsafi, Babak

AU - Moshovos, Andreas

PY - 2010/1

Y1 - 2010/1

N2 - Despite a decade of research demonstrating its efficacy, address-correlated prefetching has never been implemented in a shipping processor because it requires megabytes of metadata - too large to store practically on chip. New storage-, latency-, and bandwidth-efficient mechanisms for storing metadata off chip yield a practical design that achieves 90 percent of the performance potential of idealized on-chip metadata storage.

AB - Despite a decade of research demonstrating its efficacy, address-correlated prefetching has never been implemented in a shipping processor because it requires megabytes of metadata - too large to store practically on chip. New storage-, latency-, and bandwidth-efficient mechanisms for storing metadata off chip yield a practical design that achieves 90 percent of the performance potential of idealized on-chip metadata storage.

KW - Address-correlated prefetching

KW - Cache memories

UR - https://www.scopus.com/pages/publications/77949614728

U2 - 10.1109/MM.2010.21

DO - 10.1109/MM.2010.21

M3 - Article

SN - 0272-1732

VL - 30

SP - 50

EP - 59

JO - IEEE Micro

JF - IEEE Micro

IS - 1

M1 - 5430739

ER -

Making address-correlated prefetching practical

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this