Measurement of high electrical current density effects in solder joints

The trend in flip chip and ball grid array (BGA) packages to increase I/O counts drive the inter-connecting solder joints to be smaller in size and, thus, have higher current density. The current densities will increase further as chip voltage decreases and absolute current levels increase. The same trend in current densities in interconnecting solder joints also is occurring in flip chip power semiconductors and evolving system-on-package power processors. A physical limit to increasing current density in both microelectronics and power electronics is electromigration. Electromigration of inter-connect metal lines is the major failure phenomenon in integrated circuits, but until recently it was seldom recognized as a reliability concern for solder joints [1,2], Understanding strain evolution in the solder over time is an important step toward developing a damage mechanics mode for solder alloy under current stressing. The strain displacement in a eutectic Sn/Pb solder joint during electrical current stressing was measured with Moiré Interferometry[3] under in-situ conditions. A Finite Element (FE) simulation for thermal stressing was performed and compared with measured strain. The initial results show that the measured strain was largely due to thermal stressing versus the current density of 1.8 × 10 ² A/cm ². A second Moiré Interferometry experiment with thermal control distinguishes deformation of solder joint due to pure current stressing above 5000 A/cm ².