Skip to main navigation Skip to search Skip to main content

Methodology to achieve higher tolerance to delay variations in synchronous circuits

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

A methodology is proposed for designing robust circuits exhibiting higher tolerance to process and environmental variations. This higher tolerance is achieved by exploiting the interdependence between the setup and hold times, reducing the delay uncertainty caused by variations. An algorithm is proposed to determine the interdependent setup-hold pair of a register. A data path designed with the proposed setup-hold pair improves the overall tolerance to variations. The methodology is evaluated for several technologies to determine the overall reduction in delay uncertainty.

Original languageEnglish
Title of host publicationGLSVLSI'10 - Proceedings of the Great Lakes Symposium on VLSI 2010
Pages447-452
Number of pages6
DOIs
StatePublished - 2010
Event20th Great Lakes Symposium on VLSI, GLSVLSI 2010 - Providence, RI, United States
Duration: May 16 2010May 18 2010

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference20th Great Lakes Symposium on VLSI, GLSVLSI 2010
Country/TerritoryUnited States
CityProvidence, RI
Period05/16/1005/18/10

Keywords

  • delay uncertainty
  • environmental variation
  • process variation
  • robust circuit
  • tolerance

Fingerprint

Dive into the research topics of 'Methodology to achieve higher tolerance to delay variations in synchronous circuits'. Together they form a unique fingerprint.

Cite this