TY - GEN
T1 - Modeling fracture in dielectric stacks due to chip-package interaction
T2 - ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, InterPACK 2011
AU - Tambat, Abhishek
AU - Lin, Hung Yun
AU - Claydon, Ian
AU - Subbarayan, Ganesh
AU - Jung, Dae Young
AU - Sammakia, Bahgat
PY - 2011
Y1 - 2011
N2 - The trend towards decreasing dielectric constant of Interlayer Dielectric (ILD) materials has required significant trade-off between electrical performance and mechanical integrity of the die stack. Fracture caused by thermal stresses due to large coefficient of thermal expansion (CTE) mismatch between these materials arising during fabrication or testing are often the main driving force for failure. In this paper, we use CAD-inspired hierarchical field compositions [1] to carry out Isogeometric (meshfree) fracture simulations. We model cracks as arbitrary curves/surfaces and the crack propagation criterion is based on the evolving energy release rate (ERR) of the system. We simulate the solder reflow process to assess the impact of chip-package interaction on the reliability of ILD stacks. We use multi-level modeling to extract displacement boundary conditions for the local model of the ILD stack. Eight layers of metallization are considered in the ILD stack. We study the relative risks of replacing stronger dielectric (SiO2) with weaker dielectrics (SiCOH, ULK) on the criticality of preexisting flaws in the structure. Further, we study the impact of varying interfacial toughness values on the crack growth patterns in ILD stacks. Crack patterns reflect the propensity towards predominantly bulk failure with increasing interfacial toughness.
AB - The trend towards decreasing dielectric constant of Interlayer Dielectric (ILD) materials has required significant trade-off between electrical performance and mechanical integrity of the die stack. Fracture caused by thermal stresses due to large coefficient of thermal expansion (CTE) mismatch between these materials arising during fabrication or testing are often the main driving force for failure. In this paper, we use CAD-inspired hierarchical field compositions [1] to carry out Isogeometric (meshfree) fracture simulations. We model cracks as arbitrary curves/surfaces and the crack propagation criterion is based on the evolving energy release rate (ERR) of the system. We simulate the solder reflow process to assess the impact of chip-package interaction on the reliability of ILD stacks. We use multi-level modeling to extract displacement boundary conditions for the local model of the ILD stack. Eight layers of metallization are considered in the ILD stack. We study the relative risks of replacing stronger dielectric (SiO2) with weaker dielectrics (SiCOH, ULK) on the criticality of preexisting flaws in the structure. Further, we study the impact of varying interfacial toughness values on the crack growth patterns in ILD stacks. Crack patterns reflect the propensity towards predominantly bulk failure with increasing interfacial toughness.
UR - https://www.scopus.com/pages/publications/84860335177
U2 - 10.1115/IPACK2011-52237
DO - 10.1115/IPACK2011-52237
M3 - Conference contribution
SN - 9780791844618
T3 - ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, InterPACK 2011
SP - 317
EP - 323
BT - ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, InterPACK 2011
Y2 - 6 July 2011 through 8 July 2011
ER -