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New improved low power and high SNM single metal SRAM in 32 nm technology

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The driving forces behind the need for the development of different SRAM designs are power dissipation and delay reduction along with improvement of cell stability. SRAM cell stability assessment is traditionally based on static criteria of data stability calculated through Static Noise Margin. This paper focuses on comparison of two SRAM designs by calculation of power consumption; write delay and stability based on SNM for frequencies up to 5 GHz. The new improved single metal SRAM design is better than conventional double metal SRAM design as-on chip area utilization is reduced by 8.7%, write 1 delay by 4.26% and write 0 delay by 3.15%. Also, single metal SRAM design is slightly more stable because SNM is improved marginally from 124.16 mV to 124.36 mV which is nearly 0.16%.

Original languageEnglish
Title of host publication2014 International Conference on Computer Communication and Informatics
Subtitle of host publicationUshering in Technologies of Tomorrow, Today, ICCCI 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479923526
DOIs
StatePublished - Oct 12 2014
Event4th International Conference on Computer Communication and Informatics, ICCCI 2014 - Coimbatore, India
Duration: Jan 3 2014Jan 5 2014

Publication series

Name2014 International Conference on Computer Communication and Informatics: Ushering in Technologies of Tomorrow, Today, ICCCI 2014

Conference

Conference4th International Conference on Computer Communication and Informatics, ICCCI 2014
Country/TerritoryIndia
CityCoimbatore
Period01/3/1401/5/14

Keywords

  • Butterfly Curve
  • CMOS
  • Delay
  • Power Dissipation
  • SNM

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