On optimizing nMOS and dynamic CMOS functional cells

S. Chakravarty; Xin He; S. S. Ravi

On optimizing nMOS and dynamic CMOS functional cells

S. Chakravarty
, Xin He
, S. S. Ravi

Department of Computer Science and Engineering

University at Buffalo

SUNY Buffalo

Research output: Contribution to journal › Conference article › peer-review

Abstract

The problem of optimizing the layout of nMOS and dynamic CMOS functional cells is addressed. A simple linear-time optimal algorithm is presented for minimizing the width of such cells. A solution to width minimization results in an ordering of the FETs in L. A simple linear-time algorithm is presented for height minimization when an optimal ordering is given. There are a number of FET orderings that minimize the width of the cell. It is shown that finding an optimal FET ordering with minimum height is NP-hard even for series-parallel networks.

Original language	English
Pages (from-to)	1701-1704
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
State	Published - 1990
Event	1990 IEEE International Symposium on Circuits and Systems Part 3 (of 4) - New Orleans, LA, USA Duration: May 1 1990 → May 3 1990

Cite this

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title = "On optimizing nMOS and dynamic CMOS functional cells",

abstract = "The problem of optimizing the layout of nMOS and dynamic CMOS functional cells is addressed. A simple linear-time optimal algorithm is presented for minimizing the width of such cells. A solution to width minimization results in an ordering of the FETs in L. A simple linear-time algorithm is presented for height minimization when an optimal ordering is given. There are a number of FET orderings that minimize the width of the cell. It is shown that finding an optimal FET ordering with minimum height is NP-hard even for series-parallel networks.",

author = "S. Chakravarty and Xin He and Ravi, \{S. S.\}",

year = "1990",

language = "English",

volume = "3",

pages = "1701--1704",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "1990 IEEE International Symposium on Circuits and Systems Part 3 (of 4) ; Conference date: 01-05-1990 Through 03-05-1990",

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TY - JOUR

T1 - On optimizing nMOS and dynamic CMOS functional cells

AU - Chakravarty, S.

AU - He, Xin

AU - Ravi, S. S.

PY - 1990

Y1 - 1990

N2 - The problem of optimizing the layout of nMOS and dynamic CMOS functional cells is addressed. A simple linear-time optimal algorithm is presented for minimizing the width of such cells. A solution to width minimization results in an ordering of the FETs in L. A simple linear-time algorithm is presented for height minimization when an optimal ordering is given. There are a number of FET orderings that minimize the width of the cell. It is shown that finding an optimal FET ordering with minimum height is NP-hard even for series-parallel networks.

AB - The problem of optimizing the layout of nMOS and dynamic CMOS functional cells is addressed. A simple linear-time optimal algorithm is presented for minimizing the width of such cells. A solution to width minimization results in an ordering of the FETs in L. A simple linear-time algorithm is presented for height minimization when an optimal ordering is given. There are a number of FET orderings that minimize the width of the cell. It is shown that finding an optimal FET ordering with minimum height is NP-hard even for series-parallel networks.

UR - https://www.scopus.com/pages/publications/0025683544

M3 - Conference article

SN - 0271-4310

VL - 3

SP - 1701

EP - 1704

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 1990 IEEE International Symposium on Circuits and Systems Part 3 (of 4)

Y2 - 1 May 1990 through 3 May 1990

ER -

On optimizing nMOS and dynamic CMOS functional cells

Abstract

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