On the optimization and design of SiGe HBT cascode low-noise amplifiers

Qingqing Liang; Guofu Niu; John D. Cressler; Stewart Taylor; David L. Harame

doi:10.1016/j.sse.2004.10.002

On the optimization and design of SiGe HBT cascode low-noise amplifiers

Qingqing Liang
, Guofu Niu
, John D. Cressler
, Stewart Taylor
, David L. Harame

NY Creates Research Foundation

NY Creates

Georgia Institute of Technology
Auburn University
Intel

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

This work presents a new design methodology for inductively-degenerated cascode low-noise amplifiers using advanced epitaxial-base SiGe HBTs. IIP3 and noise figure are simulated using a calibrated linear circuit analysis and Volterra series methodology as a function of the two major design variables: emitter geometry and biasing current. Analytical IIP3 expressions with/without the CB capacitance are derived and used to explain the numerical simulation results. The cancellation among individual non-linearities is maximized at a certain I_C and emitter length combination, thus producing an IIP3 peak. The analytical expressions are in good agreement with the numerical simulation results, and can be used for robust circuit design.

Original language	English
Pages (from-to)	329-341
Number of pages	13
Journal	Solid-State Electronics
Volume	49
Issue number	3
DOIs	https://doi.org/10.1016/j.sse.2004.10.002
State	Published - Mar 2005

Keywords

Cascode
Input third-order intercept point (IIP3)
LNA
Noise figure
SiGe HBTs
Volterra series

Access to Document

10.1016/j.sse.2004.10.002

Cite this

@article{529be634d67a447799aa3f7c0a9e776e,

title = "On the optimization and design of SiGe HBT cascode low-noise amplifiers",

abstract = "This work presents a new design methodology for inductively-degenerated cascode low-noise amplifiers using advanced epitaxial-base SiGe HBTs. IIP3 and noise figure are simulated using a calibrated linear circuit analysis and Volterra series methodology as a function of the two major design variables: emitter geometry and biasing current. Analytical IIP3 expressions with/without the CB capacitance are derived and used to explain the numerical simulation results. The cancellation among individual non-linearities is maximized at a certain IC and emitter length combination, thus producing an IIP3 peak. The analytical expressions are in good agreement with the numerical simulation results, and can be used for robust circuit design.",

keywords = "Cascode, Input third-order intercept point (IIP3), LNA, Noise figure, SiGe HBTs, Volterra series",

author = "Qingqing Liang and Guofu Niu and Cressler, \{John D.\} and Stewart Taylor and Harame, \{David L.\}",

year = "2005",

month = mar,

doi = "10.1016/j.sse.2004.10.002",

language = "English",

volume = "49",

pages = "329--341",

journal = "Solid-State Electronics",

issn = "0038-1101",

publisher = "Elsevier Ltd.",

number = "3",

}

TY - JOUR

T1 - On the optimization and design of SiGe HBT cascode low-noise amplifiers

AU - Liang, Qingqing

AU - Niu, Guofu

AU - Cressler, John D.

AU - Taylor, Stewart

AU - Harame, David L.

PY - 2005/3

Y1 - 2005/3

N2 - This work presents a new design methodology for inductively-degenerated cascode low-noise amplifiers using advanced epitaxial-base SiGe HBTs. IIP3 and noise figure are simulated using a calibrated linear circuit analysis and Volterra series methodology as a function of the two major design variables: emitter geometry and biasing current. Analytical IIP3 expressions with/without the CB capacitance are derived and used to explain the numerical simulation results. The cancellation among individual non-linearities is maximized at a certain IC and emitter length combination, thus producing an IIP3 peak. The analytical expressions are in good agreement with the numerical simulation results, and can be used for robust circuit design.

AB - This work presents a new design methodology for inductively-degenerated cascode low-noise amplifiers using advanced epitaxial-base SiGe HBTs. IIP3 and noise figure are simulated using a calibrated linear circuit analysis and Volterra series methodology as a function of the two major design variables: emitter geometry and biasing current. Analytical IIP3 expressions with/without the CB capacitance are derived and used to explain the numerical simulation results. The cancellation among individual non-linearities is maximized at a certain IC and emitter length combination, thus producing an IIP3 peak. The analytical expressions are in good agreement with the numerical simulation results, and can be used for robust circuit design.

KW - Cascode

KW - Input third-order intercept point (IIP3)

KW - LNA

KW - Noise figure

KW - SiGe HBTs

KW - Volterra series

UR - https://www.scopus.com/pages/publications/12344291973

U2 - 10.1016/j.sse.2004.10.002

DO - 10.1016/j.sse.2004.10.002

M3 - Article

SN - 0038-1101

VL - 49

SP - 329

EP - 341

JO - Solid-State Electronics

JF - Solid-State Electronics

IS - 3

ER -

On the optimization and design of SiGe HBT cascode low-noise amplifiers

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this